CY7C1250V18-333BZXC Cypress Semiconductor Corp, CY7C1250V18-333BZXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1250V18-333BZXC
• Description: IC SRAM 36MBIT 333MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1250V18-333BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 333MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL may
Application Example
Figure 1
Truth Table
The truth table for the CY7C1246V18, CY7C1257V18, CY7C1248V18, and CY7C1250V18 follows.
Notes
Document Number: 001-06348 Rev. *D
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle; read data on consecutive K and
K rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
7. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
(CPU or ASIC)
symmetrically.
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
MASTER
BUS
shows the use of two DDR-II+ in an application.
Source CLK
Source CLK
Cycle Start
Addresses
R/W
DQ
Operation
DQ
A
SRAM#1
LD R/W
Figure 1. Application Example
CQ/CQ
K
ZQ
K
Stopped
R = 250ohms
L-H
L-H
L-H
K
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
the
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K for a minimum of 30
ns. However, it is not necessary for the DLL to be reset to lock to
the desired frequency. During power up, when the DOFF is tied
HIGH, the DLL gets locked after 2048 cycles of stable clock.
LD
H
X
L
L
application
R/W
H
L
X
X
CY7C1246V18, CY7C1257V18
CY7C1248V18, CY7C1250V18
DQ
D(A) at K(t + 1) ↑
Q(A) at K(t + 2) ↑
High-Z
Previous State
A
SRAM#2
LD R/W
note,
DQ
[2, 3, 4, 5, 6, 7]
DLL
CQ/CQ
K
ZQ
K
D(A + 1) at K(t + 1) ↑
Q(A + 1) at K(t + 2) ↑
High-Z
Previous State
Considerations
R = 250ohms
DQ
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