XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet
XCF128XFTG64C
Specifications of XCF128XFTG64C
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XCF128XFTG64C Summary of contents
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R DS617 (v3.0.1) January 07, 2010 Features • In-System Programmable Flash Memory Optimized for Virtex®-5 or Virtex-6 FPGA Configuration • High-Performance FPGA Bitstream Transfer up to 800 Mb/s (50 MHz × 16-bits), Ideal for PCI Express® Endpoint Applications • MultiBoot ...
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R X-Ref Target - Figure 1 Platform Flash XL READY_WAIT FPGA Design (.bit) File Notes: 1. System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the maximum configuration clock frequency, check ...
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R Flash Memory Architecture Overview Platform Flash 128- × 16) non-volatile flash memory. The device is in-system programmable with a 1.8V core (V ) power supply. A separate I enables I/O operation at ...
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R X-Ref Target - Figure 4 Parameter DS617 (v3.0.1) January 07, 2010 Product Specification Platform Flash XL High-Density Configuration and Storage Device Address 7FFFFFh 16 Kword 7FC000h 7F3FFFh 16 Kword 7F0000h 7EFFFFh Bank 64 Kword 7E0000h 78FFFFh 64 Kword 780000h ...
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R Pinout and Signal Descriptions See Figure 5 and Table 2 for a logic diagram and brief overview of the signals connected to this device. Table 2: Signal Names Signal Name Function A22-A0 Address Inputs Data Input/Outputs, DQ15-DQ0 Command Inputs ...
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R X-Ref Target - Figure DQ8 DQ1 F K DQ0 G A22 Notes: 1. See the FT64/FTG64 package specifications ...
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R Latch Enable (L) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable and inhibited when Latch Enable The Latch Enable (L) signal must ...
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R as close as possible to the package). The PCB track widths should be sufficient to carry the required V program and erase currents. PP FPGA Configuration Overview Platform Flash XL enables the rich set of FPGA configuration features without ...
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R Slave SelectMAP Configuration Mode Platform Flash XL achieves maximum configuration performance when the FPGA is in Slave SelectMAP configuration mode. In the Slave SelectMAP mode, a stable, external clock source can drive the synchronous bitstream transfer from the device ...
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R Programming Overview Programming solutions satisfying the requirements for each product phase are available for Platform Flash XL. ISE software provides integrated programming support for the FPGA design engineer in the prototyping environment. Third-party programming support is also available for ...
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R Bus Operations There are six standard bus operations that control the device: Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset (Table Bus Read Bus Read operations are used to output the contents of the Memory Array, ...
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R Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the ...
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R into Read Electronic Signature mode. Subsequent Bus Read cycles output Electronic Signature data, and the Program/Erase controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. ...
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R The only operation permitted during Blank Check is Read Status Register. Dual Operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in ...
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R Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. The command is used to program one or more Write Buffer(s) ...
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R The Program/Erase Resume command is required to restart the suspended operation. One Bus Write cycle is required to issue the Program/Erase Suspend command. After the Program/Erase Controller pauses, bits SR7, SR6 and/or SR2 of the Status Register are set ...
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R • The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. • The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be ...
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R (1) Table 7: Standard Commands Commands Read Array 1+ Read Status Register 1+ Read Electronic 1+ Signature Read CFI Query 1+ Clear Status Register 1 Block Erase 2 Program 2 (4) Buffer Program n+4 Program/Erase Suspend 1 Program/Erase Resume ...
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R Table 8: Factory Commands Command Phase Blank Check 2 Setup 2 Buffer Enhanced Program/ ≥32 Factory Program (3) Verify Exit 1 Notes Word Address in targeted bank, BKA = Bank Address, PD =Program Data ...
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R Table 10: Protection Register Locks Lock Number Address Bits bit 0 Lock 1 bit 1 80h bits bit 0 bit 1 bit 2 Lock 2 – 89h bit 13 bit 14 bit 15 X-Ref Target - ...
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R Status Register The Status Register provides information on the current or previous program or erase operations. A Read Status Register command is issued to read the contents of the Status Register, refer to "Read Status Register Command," page 14 ...
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R Controller is active; when the bit is High (set to ‘1’), the controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command was ...
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R Block Protection Status Bit (SR1) The Block Protection Status bit is used to identify if a Program or Block Erase operation tried to modify the contents of a locked or locked-down block. When this bit is High (set to ...
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R Configuration Register The Configuration Register is used to configure the type of bus access that the memory performs. Refer to page 34 for details on read operations. The Configuration Register is set through the Command Interface using the Set ...
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R Read Mode Select Bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When this bit is set to ‘1’, read operations are asynchronous; when set to ‘0’, read operations are synchronous. ...
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R Wrap Burst Bit (CR3) The Wrap Burst bit (CR3) is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 16-word boundary (wrap) or overcome the boundary (no wrap). When ...
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R Table 14: Burst Type Definition Start Address 4 Words 0-1-2-3 0 1-2-3-0 1 2-3-0-1 2 3-0-1-2 3 7-4-5 0-1-2-3 0 1-2-3-4 1 2-3-4-5 2 3-4-5-6 3 7-8-9-10 7 12-13-14-15 12 13-14-15-WAIT-16 13 14-15-WAIT-WAIT-16-17 14 ...
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R X-Ref Target - Figure A22–A0 VALID ADDRESS DQ15–DQ0 Wait CR8 = ‘0’ CR10 = ‘0’ Wait CR8 = ‘1’ CR10 = ‘0’ Wait CR8 = ‘0’ CR10 = ‘1’ Wait CR8 = ‘1’ CR10 = ...
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R X-Ref Target - Figure DDQ T VHRWZ READY_WAIT T RWRT RWHKL K A22–A0 Address not Valid DQ15–DQ0 Notes tied High. 2. Address is latched on the third rising edge ...
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R X-Ref Target - Figure 13 T RWLRWH READY_WAIT G High A22-A0 DQ15-DQ0 Dk Dn DATA VALID Notes and Dn indicate the Data valid after k and n clock cycles, respectively. 2. This figure applies ...
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R X-Ref Target - Figure 15 T PLPH PLRWL PHRWZ READY_WAIT G High A22−A0 Address not Valid DQ15−DQ0 X-Ref Target - Figure 16 T PLPH RP READY_WAIT T PHRWZ T PLRWL Low G High ...
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R Read Modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous; if the data output ...
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R The Clock signal is then halted at V Enable (G) goes High. When Output Enable goes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed at its previous location. When READY_WAIT (with CR4 = ...
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R Table 16: Dual Operations Allowed in Same Bank (Cont’d) Status of Bank Read Array Register Program Suspended Erase Suspended Notes: 1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase ...
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R Block Locking Platform Flash XL features an instant, individual block-locking scheme, allowing any block to be locked or unlocked with no latency. This locking scheme has three levels of protection: • Lock/Unlock – this first level allows software only ...
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R Table 18: Lock Status (1) Current Protection Status Program/Erase Current State Allowed 1,0,0 (2) 1,0,1 – 1,1,0 1,1,1 – 0,0,0 (2) 0,0,1 – 0,1,1 – Notes: 1. The lock status is defined by the write protect pin and by ...
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R Power-On Reset To ensure a correct power-up sequence of Platform Flash XL, the V ramp time must not be shorter than DD VDDPOR 200 μs or longer than 50 ms during power-up (see page 40). These timing ...
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R X-Ref Target - Figure 18 T VDDPOR(MIN DDPOR V DDPD Notes slow-ramping V power supply can still be below the minimum operating voltage when the READY_WAIT pin is released. In this case, the DD ...
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R First Address Latching Sequence The first address latching sequence (FALS) is one of the key features of Platform Flash XL. This particular sequence, shown in Figure 19, page 41 and Figure 21, page allows the device to latch the ...
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R X-Ref Target - Figure DDQ READY_WAIT A22–A0 DQ15–DQ0 Notes: 1. Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last. After ...
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R X-Ref Target - Figure DDQ READY_WAIT T GLRWH G High RP E Low AVRWH A22–A0 DQ15–DQ0 Figure 21: First Address Latching Sequence (FALS): Clock is Free Running Table 20: FALS Sequence Timings ...
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R Program and Erase Times and Endurance Cycles Table 21 lists both program and erase times plus the number of program/erase cycles per block. Exact erase times can vary depending on the memory array condition. The best case is when ...
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R Maximum Rating Stressing the device above the rating listed in ratings only, and proper operation of the device at these or any other conditions above those indicated in this specification is not implied. Exposure to Absolute Maximum Rating conditions ...
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R Table 24: Quality and Reliability Characteristics Symbol T Data retention DR N Program/erase cycles (Endurance Electrostatic Discharge (ESD) ESD Notes: 1. Program/erase cycles when X-Ref Target - Figure 22 V DDQ X-Ref Target ...
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R (1) Table 25: Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Notes: 1. Sampled only, not 100% tested. Table 26: DC Characteristics: Currents Symbol Parameter I Input leakage current LI I Output leakage current LO Supply ...
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R Table 27: DC Characteristics: Voltages Symbol Parameter V Input Low voltage IL V Input High voltage IH V Output Low voltage OL V Output High voltage program voltage-logic PP1 program voltage factory PPH ...
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R X-Ref Target - Figure 26 A22–A3 T AVAV A2–A0 VALID ADDRESS T AVLH L T LLLH T LLQV T ELLH E T ELQV T ELQX G T ELTV Hi-Z (1) READY_WAIT T DQ15–DQ0 Valid Address Latch Notes: 1. READY_WAIT ...
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R Table 28: Asynchronous Read AC Characteristics Symbol Alt T T AVAV AVQV ACC T T AVQV1 PAGE ( AXQX OH T ELTV ( ELQV CE ( ELQX LZ T EHTZ ...
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R X-Ref Target - Figure 27 Hi-Z DQ15–DQ0 A22–A0 VALID ADDRESS T AVLH LLKH T AVKH ( ELKH KHAX E G High W T ELTV Hi-Z READY_WAIT Address Latch Notes: 1. The number of ...
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R Table 29: Synchronous Read AC Characteristics Symbol Alt T T AVKH AVCLKH T T ELKH ELCLKH (3) T ELTV T EHEL (3) T EHTZ T T KHAX CLKHAX (4) T KHQV T CLKHQV (3) T KHTV T KHQX T ...
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R X-Ref Target - Figure 29 A22– ELKH E G High W Hi-Z DQ15–DQ0 Hi-Z (1,2) READY_WAIT Notes: 1. The READY_WAIT signal is configured to be active during wait state. READY_WAIT signal is active Low. 2. ...
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R X-Ref Target - Figure 30 Hi-Z DQ15–DQ0 A22–A0 VALID ADDRESS T AVLH L T LLKH T AVKH ( ELKH E G (2,5) Hi-Z READY_WAIT High W Notes: 1. The number of clock cycles to be inserted ...
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R X-Ref Target - Figure 31 A22–A0 BANK ADDRESS T AVLH T LLLH L T ELLH E T ELWL G T GHWL W T DVWH DQ15–DQ0 COMMAND SET-UP COMMAND Figure 31: Write AC Waveforms, Write Enable ...
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R Table 30: Write AC Characteristics, Write Enable Controlled Symbol Alt T T Address Valid to Next Address Valid AVAV WC T Address Valid to Latch Enable High AVLH (2) T Address Valid to Write Enable High AVWH T T ...
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R X-Ref Target - Figure 32 BANK ADDRESS A22– AVLH LHAX T LLLH L T ELLH W T WLEL G T GHEL E T ELEH T DVEH DQ15–DQ0 COMMAND SET-UP COMMAND Figure 32: Write ...
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R Table 31: Write AC Characteristics, Chip Enable Controlled Symbol Alt T T Address Valid to Next Address Valid AVAV WC T Address Valid to Chip Enable High AVEH T Address Valid to Latch Enable High AVLH T T Data ...
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R Table 32: Reset and Power-Up AC Characteristics Symbol Reset Low to: T PLWL Write Enable Low, T PLEL Chip Enable Low, T PLGL Output Enable Low, T PLLL Latch Enable Low Reset High to: T PHWL Write Enable Low ...
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... FTG64 = 64-ball, Fine-Pitch Thin Ball Grid Array, Pb-free Notes: 1. See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm. Valid Ordering Combinations Table 34: Valid Ordering Combinations XCF128XFTG64C DS617 (v3.0.1) January 07, 2010 Product Specification Platform Flash XL High-Density Configuration and Storage Device Parameter drops below the ...
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... Origin and Traceability Code Appendix A: Block Address Tables Table 35: Boot Block Addresses (1) Bank Parameter Bank Bank 1 DS617 (v3.0.1) January 07, 2010 Product Specification Platform Flash XL High-Density Configuration and Storage Device XCF128XFTG64C XXX XXXXX XX XXX XX YWW FT64 Ball A1 Figure 36: Marking Information # Size (Kword ...
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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 DS617 (v3.0.1) January 07, 2010 Product Specification Platform Flash XL High-Density Configuration and Storage Device # Size (Kword ...
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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 DS617 (v3.0.1) January 07, 2010 Product Specification Platform Flash XL High-Density Configuration and Storage Device # Size (Kword ...
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R Table 35: Boot Block Addresses (Cont’d) (1) Bank Bank 12 Bank 13 Bank 14 Bank 15 Notes: 1. There are two Bank Regions: Bank Region 1 contains all the banks made up of main blocks only; Bank Region 2 ...
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R Appendix B: Common Flash Interface The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from flash memory devices. This interface allows system software to query the device to determine various electrical and timing ...
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R Table 38: CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 01Bh 0017h bit BCD value in volts bit BCD value in 100 millivolts V Logic ...
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R Table 40: Primary Algorithm-Specific Extended Query Table Offset Data 0050h (P)h = 10Ah 0052h 0049h (P+3)h = 10Dh 0031h (P+4)h = 10Eh 0033h (P+5)h = 10Fh 00E6h 0003h (P+7)h = 111h 0000h (P+8)h = 112h 0000h (P+9)h = 113h ...
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R Table 41: Protection Register Information Offset Data (P+E)h = 118h 0002h (P+F)h = 119h 0080h (P+10)h = 11Ah 0000h (P+ 11)h = 11Bh 0003h (P+12)h = 11Ch 0003h (P+13)h = 11Dh 0089h (P+14)h = 11Eh 0000h (P+15)h = 11Fh ...
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R Table 44: Bank and Erase Block Region 1 Information Offset Data (P+24)h = 12Eh 0Fh (P+25)h = 12Fh 00h (P+26)h = 130h 11h (P+27)h = 131h 00h (P+28)h = 132h 00h (P+29)h = 133h 01h (P+2A)h = 134h 07h ...
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R Table 45: Bank and Erase Block Region 2 Information Offset Data (P+32)h = 13Ch 01h (P+33)h = 13Dh 00h (P+34)h = 13Eh 11h (P+35)h = 13Fh 00h (P+36)h = 140h 00h (P+37)h = 141h 02h (P+38)h = 142h 06h ...
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R Appendix C: Flowcharts and Pseudocodes X-Ref Target - Figure 37 Start (3) Write 40h or 10h Write Address & Data Read Status (3) Register NO SR7 = 1 YES Invalid SR3 = 0 Error YES NO ...
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R X-Ref Target - Figure 38 Start Write Block Address & BCh Write Block Address & CBh Read (1) Status Register NO SR7 = 1 YES YES Command Sequence SR4 = 1 SR5 = 1 NO SR5 = 0 Blank ...
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R X-Ref Target - Figure 39 Start Buffer Program E8h Command, Start Address Read Status Register NO SR7 = 1 YES (1) Write n , Start Address Write Buffer Data, Start Address YES Write ...
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R X-Ref Target - Figure 40 Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO Program Complete SR2 = 1 Write FFh Read Data YES Write FFh Read data from another address Write D0h (1) ...
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R X-Ref Target - Figure 41 Start (2) Write 20h Write Block Address & D0h Read Status (2) Register NO SR7 = 1 YES SR3 = 0 Error YES YES Command SR4, SR5 = 1 Sequence Error ...
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R X-Ref Target - Figure 42 Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block, Program, Set Configuration Register or Block Protect/Unprotect/Lock Write D0h ...
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R X-Ref Target - Figure 43 Start (1) Write 60h Write 01h, D0h or 2Fh (1) Write 90h Read Block Lock States NO Locking change confirmed? YES (1) Write FFh End Notes: 1. Any address within the bank can equally ...
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R X-Ref Target - Figure 44 Start (3) Write C0h Write Address & Data Read Status (3) Register NO SR7 = 1 YES SR3 = 0 Error YES NO Program SR4 = 0 Error YES NO Program ...
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R Start Write 80h to Address WA1 Write D0h to Address WA1 Read Status Register NO SR7 = 0 NO Initialize count SR4 = Write PDX Read Status Register Address WA1 SR3 and SR1for errors Increment ...
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R Appendix D: Command Interface State Tables Table 46: Command Interface States – Modify Table, Next State Current CI State Program Ready Ready Setup Lock/CR Setup Setup OTP IS in OTP Busy OTP Busy Busy IS in OTP busy Setup ...
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R Table 46: Command Interface States – Modify Table, Next State Current CI State Setup Ready (error Erase Busy Erase Busy Busy IS in Erase Erase Busy Erase Program Suspend Suspend ...
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R Table 46: Command Interface States – Modify Table, Next State Current CI State Buffer Suspend Suspend Suspend Program Erase Suspend (Cont’ Suspend in ES Setup Blank Check ...
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R Table 47: Command Interface States – Modify Table, Next Output State Current CI State Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load ...
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R Table 47: Command Interface States – Modify Table, Next Output State Current CI State OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Array Program Busy in Erase Suspend Buffer Program Busy in ...
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R Table 48: Command Interface States – Lock Table, Next State Current CI State Lock/CR Setup( (2) Setup (60h) Ready Lock/CR Setup Lock/CR Setup Ready (Lock error) Setup OTP Busy IS in OTP busy Setup Busy IS in Program Program ...
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R Table 48: Command Interface States – Lock Table, Next State Current CI State Lock/CR Setup( (2) Setup (60h) Setup Buffer Load 1 Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Buffer Load 2 Confirm Buffer ...
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R Table 49: Command Interface States – Lock Table, Next Output State Blank Current CI Lock/CR Check State (3) Setup ( setup 60h) (BCh) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer ...
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R Table 49: Command Interface States – Lock Table, Next Output State Blank Current CI Lock/CR Check State (3) Setup ( setup 60h) (BCh) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Eras e Suspend Buffer Program Suspend ...
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R Revision History The following table shows the revision history for this document. Date Version 12/13/07 1.0 Initial Xilinx release. 03/31/08 2.0 Added bus operations and advance device specifications: • Expanded • Added the following sections: ♦ ♦ ♦ ♦ ...
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R Date Version • See XCN09032, DS617, High-Density Configuration and Storage Device Data Sheet Revision, 11/30/09 3.0 v3.0, for detailed product revisions: • Product change from preliminary to production phase. • Updated • Removed references and placeholders to V • ...