XC17S100APD8C Xilinx Inc, XC17S100APD8C Datasheet - Page 2
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XC17S100APD8C
Manufacturer Part Number
XC17S100APD8C
Description
IC PROM SER 100000 C-TEMP 8-DIP
Manufacturer
Xilinx Inc
Specifications of XC17S100APD8C
Programmable Type
OTP
Memory Size
1Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Capacitance, Input
10 pF
Capacitance, Output
10 pF
Current, Input, Leakage
±10 μA
Current, Operating
15 mA
Current, Output, Leakage
±10
Data Retention
20 yrs.
Density
781216
Interface
Parallel Bus
Memory Type
PROM
Organization
1M×8
Package Type
PDIP
Temperature, Operating
0 to +70 °C
Time, Address Setup
25
Time, Rise
50 ms
Voltage, Input, High
3.3 V
Voltage, Input, Low
0.8 V
Voltage, Output, High
2.4 V
Voltage, Output, Low
0.4 V
Voltage, Supply
3.3 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC17S100APD8C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Pin Description
Pins not listed are no connects.
Pinout Diagrams
DS078 (v1.10) June 25, 2007
Product Specification
(OE/RESET)
RESET/OE
Pin Name
DATA
GND
CLK
V
CE
CC
OE/RESET
OE/RESET
DATA (D0)
DATA(D0)
R
CLK
CLK
NC
NC
NC
NC
NC
NC
CE
CE
(PD8/PDG8)
(VO8/VOG8)
VOIC/TSOP
8-pin
PDIP
and
7, 8
1
2
3
4
5
1
10
2
3
4
5
6
7
8
9
1
2
3
4
Top View
PD8/PDG8
VO8/VOG8
Top View
SO20
(SO20)
20-pin
18, 20
SOIC
10
11
1
3
8
20
19
18
17
16
15
14
13
12
11
8
7
6
5
ds078_04_061805
ds078_05_061805
VCC
VCC
NC
GND
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
(VQ44)
44-pin
VQFP
18, 41
38, 35
40
43
13
15
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
www.xilinx.com
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
When High, this input holds the address counter reset and puts the
DATA output in a high-impedance state. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion,
this document describes the pin as RESET/OE, although the opposite
polarity is possible on all devices. When RESET is active, the address
counter is held at zero, and the DATA output is in a high-impedance
state. The polarity of this input is programmable. The default is active-
High RESET, but the preferred option is active Low RESET, because it
can be connected to the FPGAs INIT pin and a pull-up resistor.
The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer software.
Third-party programmers have different methods to invert this pin.
When High, this pin resets the internal address counter, puts the DATA
output in a high-impedance state, and forces the device into low-I
standby mode.
GND is the ground connection.
The V
CC
pins are to be connected to the positive voltage supply.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
Pin Description
Top View
VQ44
33
32
31
30
29
28
27
26
25
24
23
ds073_06_061805
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CC
2