MAX6959AAEE+ Maxim Integrated Products, MAX6959AAEE+ Datasheet - Page 6
![IC DRVR DSPL LED 16-QSOP](/photos/6/61/66127/175-16-qsop_sml.jpg)
MAX6959AAEE+
Manufacturer Part Number
MAX6959AAEE+
Description
IC DRVR DSPL LED 16-QSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6958AAEE.pdf
(19 pages)
Specifications of MAX6959AAEE+
Display Type
LED
Configuration
7 Segment + 2 Annunciators
Interface
SMBus (2-Wire/I²C)
Digits Or Characters
4 Digits
Current - Supply
5.9mA
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Number Of Digits
4
Number Of Segments
36
Low Level Output Current
275 mA
High Level Output Current
30 mA
Operating Supply Voltage
3 V to 5.5 V
Maximum Supply Current
6.7 mA
Maximum Power Dissipation
667 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX6958/MAX6959 have the same LED drive
capability, four common-cathode digits of nine seg-
ments per digit. The MAX6959 additionally contains two
logic input ports, INPUT1 and INPUT2. Each input port
can be individually configured as either a general-pur-
pose input port that is read through the serial interface,
or as a keyscan input. In keyscan mode, the input is
used to read and automatically debounce four key
switches. A maximum of eight key switches can be
read if both INPUT1 and INPUT2 are assigned to
keyscanning.
The MAX6958's SEG9 output is preconfigured as the
9th LED segment output. The IRQ/SEG9 output on the
MAX6959 can be configured as either an open-drain
logic output or the 9th segment output. This logic out-
put serves as either a general-purpose logic output, set
through the serial interface, or an interrupt (IRQ) output
that alerts a microcontroller of debounced key-switch
events. Key-switch status can also be obtained by
polling the internal status registers at any time.
Use the Option bit in the configuration register to detect
whether a MAX6958 or MAX6959 is present. The option
bit allows host software to establish whether a high-end
front panel (using the MAX6959 for keyscan support) or
a low-end panel (using a MAX6958 and no key switch-
es) is fitted to a product.
The MAX6958/MAX6959 operate as a slave that sends
and receives data through a 2-wire interface. The inter-
face uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX6958/MAX6959, and generates the SCL clock that
synchronizes the data transfer (Figure 1).
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Figure 1. 2-Wire Serial Interface Timing Details
6
_______________________________________________________________________________________
SDA
SCL
t
HD, STA
CONDITION
START
Differences Between MAX6958
t
t
LOW
LOW
t
R
t
HIGH
t
SU, DAT
t
Serial Interface
F
Serial Addressing
and MAX6959
t
HD, DAT
t
SU, STA
REPEATED START
CONDITION
The MAX6958/MAX6959 SDA line operates as both an
input and an open-drain output. A pullup resistor, typi-
cally 4.7kΩ, is required on the SDA bus. The MAX6958/
MAX6959 SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on the SCL bus if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START condition
(Figure 2) sent by a master, followed by the MAX6958/
MAX6959 7-bit slave address plus
or more data bytes, and finally a STOP condition
(Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 2).
Figure 2. Start and Stop Conditions
SDA
SCL
CONDITION
START
t
HD, STA
S
t
SU, STO
Start and Stop Conditions
CONDITION
STOP
R/W bit (Figure 3), 1
t
BUF
CONDITION
START
CONDITION
STOP
P