PCA9622DR,118 NXP Semiconductors, PCA9622DR,118 Datasheet
PCA9622DR,118
Specifications of PCA9622DR,118
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PCA9622DR,118 Summary of contents
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PCA9622 16-bit Fm+ I Rev. 03 — 31 August 2009 1. General description The PCA9622 dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM ...
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... NXP Semiconductors 2. Features I 16 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off ...
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... NXP Semiconductors 3. Applications I RGB or RGBA LED drivers I LED status information I LED displays I LCD backlights I Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark [1] PCA9622BS P9622 PCA9622DR PCA9622DR [1] HVQFN32 package under development. PCA9622_3 Product data sheet ...
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PCA9622 SCL INPUT FILTER SDA POWER- RESET V SS PWM REGISTER X BRIGHTNESS CONTROL 24.3 kHz 97 kHz 25 MHz OSCILLATOR OE Remark: Only one LED output shown for clarity. Fig 1. Block diagram of PCA9622 A0 A1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning LED0 7 8 LED1 PCA9622DR LED2 LED3 11 12 LED4 13 LED5 LED6 16 LED7 Fig 2. Pin configuration for TSSOP32 6.2 Pin description Table 2. Symbol LED0 LED1 V SS LED2 LED3 LED4 LED5 V SS LED6 LED7 LED8 PCA9622_3 Product data sheet ...
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... NXP Semiconductors Table 2. Symbol LED9 V SS LED10 LED11 LED12 LED13 V SS LED14 LED15 SCL SDA V DD [1] HVQFN32 package supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 7. Functional description Refer to 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. There are a maximum of 128 possible programmable addresses using the 7 hardware address pins. Two of these addresses, Software Reset and LED All Call, cannot be used because their default power-up state is ON, leaving a maximum of 126 addresses ...
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... NXP Semiconductors 7.1.2 LED All Call I • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I • At power-up, LED All Call I E0h (R E1h (R sent by the master. See Section 7.3.8 “ALLCALLADR, LED All Call I Remark: The default LED All Call I ...
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... NXP Semiconductors 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9622, which will be stored in the Control register. The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment fl ...
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... NXP Semiconductors AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I blinking change. AI[2:0] = 111 is used when individual and global changes must be performed during the 2 same I same time. Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits. ...
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... NXP Semiconductors [1][2] Table 4. Register summary Register number (hex [1] Only D[4: 0000 to 1 1011 are allowed and will be acknowledged. D[4: 1100 to 1 1111 are reserved and will not be acknowledged. [2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation. ...
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... NXP Semiconductors 7.3.2 Mode register 2, MODE2 Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access 7 - read only 6 - read only 5 DMBLNK R/W 4 INVRT R/W 3 OCH R/W [1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9622. Applicable to registers from 02h (PWM0) to 17h (LEDOUT) only ...
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... NXP Semiconductors 7.3.4 GRPPWM, group duty cycle control Table 8. Legend: * default value Address 12h When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘ ...
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... NXP Semiconductors 7.3.6 LEDOUT0 to LEDOUT3, LED driver output state Table 10. Legend: * default value. Address 14h 15h 16h 17h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx = 11 — ...
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... NXP Semiconductors Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses (MODE1 register). Only the 7 MSBs representing the I register is a read-only bit (0). When SUBx is set to logic 1, the corresponding I either ...
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... NXP Semiconductors Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. 7.5 Power-on reset When power is applied to V condition until V PCA9622 registers and I zeroes) causing all the channels to be deselected. Thereafter, V ...
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... NXP Semiconductors 7.7 Individual brightness control with group dimming/blinking A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs): • ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 10. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 12. Write to a specific register slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave Fig 13. Write to all registers using the Auto-Increment feature ...
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... NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP from master condition Fig 15. Read all registers using the Auto-Increment feature slave address sequence (A) ...
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... NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE (1) OE requires pull-up resistor if control signal from the master is open-drain C-bus address = 0010 101x. Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. ...
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... NXP Semiconductors 10.1 Junction temperature calculation A device junction temperature can be calculated when the ambient temperature or the case temperature is known. When the ambient temperature is known, the junction temperature is calculated using Equation 4 power dissipation amb where junction temperature j T amb R th(j- (device) total power dissipation ...
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... NXP Semiconductors 10.1.1 Example known R th(j-a) T amb LED output low voltage (LED V LED output current per channel = 80 mA Number of outputs = 16 I DD(max) V DD(max C-bus clock (SCL) maximum sink current = C-bus data (SDA) maximum sink current = Find P – output total power = 80 mA – ...
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... NXP Semiconductors 1. Find P – output current (60 mA – output current (50 mA – output current (40 mA – output current (20 mA – output current (1 mA Output total power = 341.5 mW – chip core power consumption = 18 mA – SCL power dissipation = 25 mA – SDA power dissipation = 25 mA ...
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... NXP Semiconductors Table 14. Measurement amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb ...
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... NXP Semiconductors 13. Static characteristics Table 16. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors [2] Each bit must be limited to a maximum of 100 mA and the total package limited to 1600 mA due to internal busing limits (A) 3.0 V 2.3 V 0.15 0.05 0.05 0.05 0. amb amb Fig 18. V versus PCA9622_3 Product data sheet 002aae507 0. (A) 0.15 0.05 0.05 ...
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... NXP Semiconductors 14. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between BUF a STOP and START condition t hold time (repeated) HD;STA START condition t set-up time for a SU;STA repeated START condition t set-up time for STOP SU;STO condition ...
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... NXP Semiconductors [ minimum time for SDA data out to be valid following SCL LOW. VD;DAT [3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V bridge the undefined region of SCL’s falling edge. [4] The maximum t for the SDA and SCL bus lines is specifi ...
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... NXP Semiconductors 15. Test information Fig 21. Test circuitry for switching times PCA9622_3 Product data sheet V I PULSE GENERATOR R = Load resistor for LEDn. R for SDA and SCL > less current Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z T Rev. 03 — ...
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... NXP Semiconductors 16. Package outline TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0. pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 20. Acronym CDM DUT ESD FET HBM 2 I C-bus LED LCD LSB MM MSB ...
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... NXP Semiconductors 20. Revision history Table 21. Revision history Document ID Release date PCA9622_3 20090831 • Modifications: Table 1 “Ordering “SOT617-3” • Figure 3 “Pin configuration for • Section 7.4 “Active LOW output enable • Figure 17 “Typical • Added (new) • Section 11 “Limiting – ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 7 2 7.1.2 LED All Call I C-bus address . . . . . . . . . . . . . . ...