HCPL-316J Avago Technologies US Inc., HCPL-316J Datasheet - Page 23

OPTOCOUPLER GATE DRV 2A 16-SOIC

HCPL-316J

Manufacturer Part Number
HCPL-316J
Description
OPTOCOUPLER GATE DRV 2A 16-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet

Specifications of HCPL-316J

Configuration
High-Side
Input Type
Differential
Delay Time
300ns
Current - Peak
2.5A
Number Of Configurations
1
Number Of Outputs
1
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
No. Of Channels
1
Isolation Voltage
3.75kV
Optocoupler Output Type
Gate Drive
Input Current
22mA
Output Voltage
30V
Opto Case Style
SOIC
No. Of Pins
16
Propagation Delay Low-high
0.5µs
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
High Side Voltage - Max (bootstrap)
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
516-1130-5

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Slow IGBT Gate Discharge During Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the HCPL-316J output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn off, the large
output pull-down device remains off until the output
voltage falls below V
pull down device clamps the IGBT gate to V
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT ca-
pacitor. The nominal blanking time is calculated in terms
of external capacitance (C
age (V
= C
with the recommended 100 pF capacitor is 100 pF * 7 V
/ 250 μA = 2.8 μsec. The capacitance value can be scaled
slightly to adjust the blanking time, though a value small-
er than 100 pF is not recommended. This nominal blank-
ing time also represents the longest time it will take for
the HCPL-316J to respond to a DESAT fault condition. If
the IGBT is turned on while the collector and emitter are
shorted to the supply rails (switching into a short), the
soft shut-down sequence will begin after approximately
3 μsec. If the IGBT collector and emitter are shorted to
the supply rails after the IGBT is already on, the response
time will be much quicker due to the parasitic parallel
capacitance of the DESAT diode. The recommended 100
pF capacitor should provide adequate blanking as well
as fault response times for most applications.
23
BLANK
DESAT
x V
), and DESAT charge current (I
DESAT
/ I
EE
CHG
+ 2 Volts, at which time the large
. The nominal blanking time
BLANK
), FAULT threshold volt-
CHG
EE
.
) as t
BLANK
Under Voltage Lockout
The HCPL-316J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the HCPL-316J output low
during power-up. IGBTs typically require gate voltages
of 15 V to achieve their rated V
voltages below 13 V typically, their on-voltage increases
dramatically, especially at higher currents. At very low
gate voltages (below 10 V), the IGBT may operate in the
linear region and quickly overheat. The UVLO function
causes the output to be clamped whenever insufficient
operating supply (V
V
clamp is released to allow the device output to turn on
in response to input signals. As V
(at some level below V
circuitry becomes active. As V
(above V
time the UVLO clamp is released, the DESAT protection
is already active. Therefore, the UVLO and DESAT FAULT
DETECTION features work together to provide seamless
protection regardless of supply voltage (V
UVLO+
(the positive-going UVLO threshold), the UVLO
UVLO+
), the UVLO clamp is released. Before the
CC2
UVLO+
) is applied. Once V
), first the DESAT protection
CC2
CC2
CE(ON)
is further increased
is increased from 0 V
voltage. At gate
CC2
CC2
).
exceeds

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