HCPL-316J Avago Technologies US Inc., HCPL-316J Datasheet - Page 27

• Manufacturer Part Number: HCPL-316J
• Description: OPTOCOUPLER GATE DRV 2A 16-SOIC
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-316J

• Configuration: High-Side
• Input Type: Differential
• Delay Time: 300ns
• Current - Peak: 2.5A
• Number Of Configurations: 1
• Number Of Outputs: 1
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• No. Of Channels: 1
• Isolation Voltage: 3.75kV
• Optocoupler Output Type: Gate Drive
• Input Current: 22mA
• Output Voltage: 30V
• Opto Case Style: SOIC
• No. Of Pins: 16
• Propagation Delay Low-high: 0.5µs
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 516-1130-5

Auto-Reset
As shown in Figure 72, when the inverting V
connected to ground (non-inverting configuration), the
HCPL-316J can be configured to reset automatically by
connecting RESET to V
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no effect. Following a fault condition, the
gate driver remains in the latched fault state until the
gate control signal changes to the ‘gate low’ state and
resets the fault latch. If the gate control signal is a con-
tinuous PWM signal, the fault latch will always be reset
by the next time the input signal goes high. This config-
uration protects the IGBT on a cycle-by-cycle basis and
automatically resets before the next ‘on’ cycle. The fault
outputs can be wire ‘OR’ed together to alert the micro-
controller, but this signal would not be used for control
purposes in this (Auto-Reset) configuration. When the
HCPL- 316J is configured for Auto-Reset, the guaranteed
minimum FAULT signal pulse width is 3 μs.
Figure 71. Global-shutdown, global reset configuration.
Figure 73a. Safe hardware reset for noninverting input
configuration (automatically resets for every V
27
TO OTHER
CONNECT
μC
μC
RESETS
TO OTHER
CONNECT
V
RESET
FAULT
FAULTS
IN+
/
+
–
V
CC
IN+
1
2
3
4
5
6
7
8
. In this case, the gate control
1
2
3
4
5
6
7
8
V
V
V
GND1
RESET
FAULT
V
V
IN+
IN-
CC1
LED1+
LED1-
V
V
V
GND1
RESET
FAULT
V
V
IN+
IN-
CC1
LED1+
LED1-
IN+
HCPL-316J
HCPL-316J
input).
IN-
input is
Resetting Following a Fault Condition
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must first
be asserted low in order to release the internal fault
latch and reset the FAULT output (high). Prior to assert-
ing the RESET pin low, the input (V
must be configured for an output (V
can be handled directly by the microcontroller or by
hardwiring to synchronize the RESET signal with the ap-
propriate input signal. Figure 73a shows how to connect
the RESET to the V
the noninverting input configuration. Figure 73b shows
how to configure the V
signal from the microcontroller causes the input to be
in the “output-off” state. Similarly, Figures 73c and 73d
show automatic RESET and microcontroller RESET safe
configurations for the inverting input configuration.
Figure 72. Auto-reset configuration.
Figure 73b. Safe hardware reset for noninverting input
configuration.
μC
μC
RESET
FAULT
V
IN+
+
–
HCPL-316J fig 72
V
IN+
CC
signal for safe automatic reset in
IN+
1
2
3
4
5
6
7
8
/RESET signals so that a RESET
1
2
3
4
5
6
7
8
V
V
V
GND1
RESET
FAULT
V
V
IN+
IN-
CC1
LED1+
LED1-
V
V
V
GND1
RESET
FAULT
V
V
IN+
IN-
CC1
LED1+
LED1-
HCPL-316J
IN
HCPL-316J
) switching signals
OL
) low state. This