ISO1H802G Infineon Technologies, ISO1H802G Datasheet - Page 9

• Manufacturer Part Number: ISO1H802G
• Description: IC SWITCH HISIDE 8CH DSO-36
• Manufacturer: Infineon Technologies
• Series: ISOFACE™r
• Type: High Sider

Specifications of ISO1H802G

• Input Type: Parallel
• Number Of Outputs: 8
• On-state Resistance: 150 mOhm
• Current - Output / Channel: 700mA
• Current - Peak Output: 1.4A
• Voltage - Supply: 15 V ~ 30 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000386327

CS makes any transition. The number of clock pulses
will be counted during a chip select cycle. The received
data will only be accepted, if exactly an integer multiple
of 8 clock pulses were counted during CS is active.
SI - Serial input. Serial data bits are shifted in at this pin,
the most significant bit first. SI information is read in on
the rising edge of the SCLK. Input data is latched in the
shift register and then transferred to the control buffer
of the output stages.
SO - Serial output. SO is in a high impedance state until
the CS pin goes to a logic low state. The data of the
internal shift register are shifted out serially at this pin.
The most significant bit will appear at first. The further
bits will appear following the falling edge of SCLK.
3.5.2
3.5.2.1
Each IC with a SPI is controlled individually and
independently by an SPI master, as in a directional
point-to-point communication.The port requirements
for this topology are the greatest, because for each
controlled IC an individual SPI at the µC is needed
(SCLK, CS, SI). All ICs can be
simultaneously with the full SPI bandwidth.
Figure 8
Datasheet
µC
SPI
1
SPI
n
Tx a1
Tx a2
Tx n1
Tx n2
CLK
CLK
Number of addressed ICs = n
Number of necessary control and data ports = 3 n
Individual ICs are addressed by the chip select
SPI Bus Concepts
Independent Individual Control
Individual independent control of each
IC with SPI
IC1
ICn
SPI -
Interface
SPI -
Interface
SCLK
CS
SI
SO
SCLK
CS
SI
SO
addressed
Output
lines
Output
lines
9
3.5.2.2
Fig. 11 is called a daisy-chain. For this type of bus-
topology only one SPI interface of the µC for two or
more ICs is needed. All ICs share the same clock and
chip select port of the SPI master. That is all ICs are
active and addressed simultaneously. The data out of
the µC is connected to the SI of the first IC in the line.
Each SO of an IC is connected to the SI of the next IC
in the line.
Figure 9
The µC feeds to data bits into the SI of IC1 (first IC in
the chain). The bits coming from the SO of IC1 are
directly shifted into the SI of the next IC. As long as the
chip select is inactive (logic high) all the IC SPIs ignore
the clock (SCLK) and input signals (SI) and all outputs
(SO) are in tristate. As long as the chip select is active
the SPI register works as a simple shift register. With
each clock signal one input is shifted into the SPI
register (SI), each bit in the shift register moves one
position further within the register, and the last bit in the
SPI shift register is shifted out of SO. This continuous
as long as the chip select is active (logic low) and clock
signals are applied. The data is then only taken over to
the output buffers of each IC when the CS signal
changes to high from low and recognized as valid data
by the internal modulo counter.
The connection of different ICs and a µC as shown in
µC
SPI
1
Tx a1
Tx a2
CLK
Number of addressed ICs = n
Number of necessary control and data ports = 3
All ICs are addressed by the common chip select
Daisy-chain Configuration
SPI bus all ICs in a “daisy chain”
configuration
Functional Description
Version 2.4, 2009-09-16
IC1
ICn
SPI -
Interface
SPI -
Interface
SCLK
CS
SI
SO
SCLK
CS
SI
ISOFACE
ISO1H802G
Output
lines
Output
lines
TM