NCP1631DR2G ON Semiconductor, NCP1631DR2G Datasheet - Page 10

• Manufacturer Part Number: NCP1631DR2G
• Description: IC CTLR PFC INTERLEAVED 16SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1631DR2G

• Mode: Critical Conduction (CRM), Discontinuous Conduction (DCM)
• Frequency - Switching: 130kHz
• Current - Startup: 100µA
• Voltage - Supply: 10 V ~ 15 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(V
Hence, the line current absorbed by each phase is:
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped.
operation that is just a particular case of this functioning
where
(V
adapts to the conditions and jumps from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
proportional to the square of the line magnitude. Its value
is however programmed by the pin 3 resistor to adjust the
available on−time as defined by the T
of the data sheet.
is an OVP condition or a skip sequence, not to
over−dimension V
OVP sequence or a skipped cycle would be viewed as a
“normal” dead−time phase by the circuit and V
inappropriately increase to compensate it. (Refer to
Figure 7).
Given the regulation low bandwidth of the PFC systems,
One can note that this analysis is also valid for CrM
The charging current I
From these data, we can deduce:
The “V
CONTROL
TON
Figure 6. PWM Circuit and Timing Diagram
=V
(t
TON
REGUL
I
where:
3
in(phase1)
=0),
) and then (V
processing circuit” is “informed” when there
t
). That is why the NCP1631 automatically
1
+ T
which
k + constant +
TON
+ I
on
in(phase2)
in that conditions. Otherwise, an
(ms) + 50 n
REGUL
t
leads
is internally processed to be
) are slow varying signals.
+ k V
to
V
on1
C
R
pin7
in
t
V
2 L I
t
to T
2
REGUL
(t
2
1
+t
t
on4
2
=T
parameters
TON
sw
)
−> V ton d u ring (t1+t2)
−> 0 V d u ring t3 (d e a d −time)
−> V ton *(t1+t2)/T in average
http://onsemi.com
(eq. 6)
(eq. 7)
would
and
IN 1
V
10
REGUL
The integrator OA1 amplifies the error between V
voltage) is 1 V and R
on−time is 20 ms as given by parameter T
Since:
where k
network
(see Brown−out section)
average input power:
IN1 so that in average, (V
grounded when the circuit is in OFF state to discharge the
capacitor C1 and initialize it for the next active phase.
compared to V
the start−up phase (pfcOK low) and if V
brown−out block is high (refer to brown−out section for
more information).
R1
From this equation, we can check that if V
We can deduce the total input current value and the
The output of the “V
Finally, the “V
Figure 7. V
+
−
0.5*
(I se nse
− 210 m)
V
T
V
timing capacitor
s aw −too th
BO
on
OA1
REGUL(max)
pin7
C1
+
k
OC P
I
is the scale down factor of the BO sensing
in(rms)
+
BO
Vton
S2
S1
C
P
REGUL
2 2 V
t
+
V
in,avg
TON
TON
REGUL
I
^
R
t
+ 1.66 V
bo1
” is not allowed to be further increased
p
Processing Circuit
26.9 @ 10
^
TON
in(rms)
t
(high during dead−time)
when the circuit has not completed
R
is 20 kW (I
) R
bo2
26.9 @ 10
*(t
TON
PWM
comparator
+
−
S3
1
(R
(R
k
bo2
+t
BO
2
t
t
)
)
12
)/T
processing circuit” is also
2
2
DT
V
V
L k
sw
REGUL
REGUL
12
to PWM latch
) equates V
pin3
BO
L k
2
BO
V
= 50 mA) that the
in,rms
BOcomp
on1
REGUL
2
SKIP
OV P
OF F
V
(from BO block)
BOcomp
.
REGUL
pfcOK
In−rus h
and
pin7
from the
.
(eq. 8)
(eq. 9)
(BO