LP3971SQ-2G16/NOPB National Semiconductor, LP3971SQ-2G16/NOPB Datasheet
LP3971SQ-2G16/NOPB
Specifications of LP3971SQ-2G16/NOPB
LP3971SQ-2G16
LP3971SQ-2G16TR
Related parts for LP3971SQ-2G16/NOPB
LP3971SQ-2G16/NOPB Summary of contents
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... LDO 2 150 mA — LDO 3 150 mA — LDO 4 150 mA — LDO 5 370 mA ■ 100 mV (typ) dropout © 2008 National Semiconductor Corporation Features ■ Compatible with advanced applications processors requiring DVM (Dynamic Voltage Management) ■ Three buck regulators for powering high current processor functions or I/O's ■ ...
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Simplified Application Circuit www.national.com 20180701 2 ...
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The lines are pulled up via a I/O source — V LDO4, 5 can either be powered from main battery source buck regulator 20180728 www.national.com ...
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Connection Diagrams and Package Mark Information Note: Circle marks pin 1 position. Note: The actual physical placement of the package marking will vary from part to part. (*) UZTTY format: 'U' — wafer fab code; 'Z' _ assembly code; 'XY' ...
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... Voltage P55A LP3971SQX-P55A Voltage B510 LP3971SQ-B510 Voltage B510 LP3971SQX-B510 Voltage G824 LP3971SQ-G824 Voltage G824 LP3971SQX-G824 Voltage Q418 LP3971SQ-Q418 Voltage Q418 LP3971SQX-Q418 Voltage 2G16 LP3971SQ-2G16 Voltage 2G16 LP3971SQX-2G16 Voltage O509 LP3971SQ-O509 Voltage O509 LP3971SQX-O509 Voltage 7848 LP3971SQ-7848 Voltage 7848 LP3971SQX-7848 Voltage 8858 ...
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Default V Coding OUT www.national.com Z Default V OUT 0 1.3 1 1.8 2 2.5 3 2.8 4 3.0 5 3.3 6 1.0 7 1.4 8 1.2 9 1.25 A 1.35 6 ...
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Pin Descriptions Pin # Name I/O 1 PWR_ON I 2 nTEST_JIG I 3 SPARE I 4 EXT_WAKEUP O 5 FB1 LDO1 O OUT 8 V LDO2 O OUT 9 nRSTI I 10 GND1 ...
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Pin # Name I/O 34 BGND1,2 SYNC I 36 SYS_EN I 37 PWR_EN I 38 PGND1 G 39 SW1 O 40 VIN Buck1 I A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. All Inputs GND to GND SLUG Junction Temperature (T ) J-MAX Storage Temperature Power Dissipation (T = 70°C) (Note 3) A Junction-to-Ambient Thermal Resistance θ (Note 3) ...
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... SYS_EN 1.35 PWR_EN 1.1 PWR_EN 1.8 PWR_EN 1.4 PWR_EN 1.35 PWR_EN 3.3 SYS_EN 3.3 SYS_EN 1.8 SYS_EN 3.3 SYS_EN LP3971SQ-G824 LP3971SQ-Q418 No Track 2.8 No Track 2.8 SYS_EN 2.5 SYS_EN 3.0 SYS_EN 2.5 SYS_EN 3.0 SYS_EN 3.3 PWR_EN 3.3 SYS_EN 3.0 SYS_EN 1.2 PWR_EN 2 ...
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... SYS_EN Version Enable 2.8 LDO_RTC 3.0 LDO1 2.6 LDO2 3.3 LDO3 1.2 LDO4 1.8 LDO5 1.2 BUCK1 1.2 BUCK2 3.0 BUCK3 11 LP3971SQ-8858 No Track 2.8 SYS_EN 3.3 SYS_EN 3.3 SYS_EN 3.3 SYS_EN 1.2 SYS_EN 1.8 PWR_EN 1.2 PWR_EN 1.2 SYS_EN 3.3 www.national.com ...
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LDO RTC Unless otherwise noted 3.6V normal type apply for T = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, J −40°C to +125°C. (Notes ...
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LDO Unless otherwise noted 3.6V normal type apply for T = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, J −40°C to +125°C. (Notes 2, ...
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LDO1 Line Regulation V = 1.8 volts volts Load = 100 mA OUT IN Enable Start-up time (LDO1) LDO1 channel 2 LDO4 Channel 1 Sys_enable from 0 volts Load = 100mA www.national.com LDO1 Load Transient V ...
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Buck Converters SW1, SW2, SW3 Unless otherwise noted 3.6V normal type apply for T = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, J −40°C to +125°C. (Notes 2, ...
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3.5 volts V = 1.4 volts Forced PWM IN OUT Load Transient 3 3 – 100 mA load IN OUT Startup Startup into PWM Mode 980 mA [channel 1.4 ...
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Back-Up Charger Electrical Characteristics Unless otherwise noted 3.6V. Typical values and limits appearing in normal type apply for T IN BATT in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. ...
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Logic Inputs and Outputs DC Operating Conditions Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI's) Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage IH I Input Leakage Current LEAK Logic Outputs (nRSTO, ...
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Compatible Serial Interface Electrical Specifications (SDA and SCL) Unless otherwise noted 3.6V. Typical values and limits appearing in normal type apply for T IN boldface type apply over the entire junction temperature range for operation, ...
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Buck Converter Operation DEVICE INFORMATION The LP3971 includes three high efficiency step down DC-DC switching buck converters. Using a voltage mode architecture with synchronous rectification, the buck converters have the ability to deliver up to 1600 mA depending on the ...
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FIGURE 2. Typical PFM Operation During PFM operation, the converter positions the output volt- age slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. ...
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SHUTDOWN MODE During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be open in shutdown to discharge the output. When the converter is enabled, EN, soft start is activated. ...
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Compatible Interface DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when ...
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Write Cycle Read Cycle When a READ function accomplished, a WRITE function must precede the READ function as follows write (SDA = “0” read (SDA = “1”) ack = acknowledge (SDA pulled down ...
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LP3971 Register Definitions CONTROL REGISTERS Register Register Read/ Address Name Write 8h'02 ISR R 8h'07 SCR1 R/W 8h'0B BBCC R/W 8h'0E SCR2 R/W 8h'10 BOVEN R/W 8h'11 BOVSR R 8h'12 LDOEN R/W 8h'13 LDOVS ...
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Bit Access Name 1 R WUPT 0 R WUPS SYSTEM CONTROL REGISTER 1 (SCR1) 8H'07 Bit 7 Designation BPSEN Reset Value 0 Note: ** denotes EPROM programmable registers for default value. SYSTEM CONTROL REGISTER 1 (SCR1) 8H'07 DEFINITIONS Bit Access ...
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BACKUP BATTERY CHARGER CONTROL REGISTER (BBCC) 8H'0B Bit Designation Reset Value BACKUP BATTERY CHARGER CONTROL REGISTER (BBCC) 8H'0B DEFINITIONS Bit Access 7 R/W 6 --- 5:3 R/W 2 R/W 1:0 R NBUB CNBFL Name ...
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SYSTEM CONTROL REGISTER (SCR2) 8H'0E Bit 7 Designation BBCS Reset Value 1 Note: ** denotes EPROM programmable registers for default value. SYSTEM CONTROL REGISTER (SCR2) 8H'0E DEFINITIONS Bit Access Name 7 R/W BBCS Sets GPIO1 as control input for Back ...
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BUCKS OUTPUT VOLTAGE ENABLE REGISTER (BOVEN) 8H'10 Bit 7 Designation Reserved Reset Value 0 Note: ** denotes EPROM programmable registers for default value. BUCKS ENABLE REGISTER (BOVEN) 8H'10 DEFINITIONS Bit Access Name — — 7 Reserved 6 R/W B2ENC Connects ...
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LDO OUTPUT VOLTAGE ENABLE REGISTER (LDOEN) 8H'12 Bit 7 6 Designation L5EC** L4EC** Reset Value 0** 0** Note: ** denotes EPROM programmable registers for default value. LDO OUTPUT VOLTAGE ENABLE REGISTER (LDOEN) 8H'12 DEFINITIONS Bit Access Name 7 R/W L5EC ...
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Bit Access Name 2 R LDO2_OK LDO_2 Output Voltage Status LDO1_OK LDO_1 Output Voltage Status — — 0 Reserved VOLTAGE CHANGE CONTROL REGISTER 1 (V Bit ...
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BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) 8H'23 Bit 7 Designation Reset Value 0 Note: ** denotes EPROM programmable registers for default value. BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) 8H'23 DEFINITIONS Bit Access Name — — 7:5 Reserved 4:0 R/W B1OV ...
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BUCK 1 VOLTAGE RAMP CONTROL REGISTER (B1RC) 8H'25 Bit Designation Reset Value BUCK 1 VOLTAGE RAMP CONTROL REGISTER (B1RC) 8H'25 DEFINITIONS Bit Access Name — — 7:5 Reserved 4:0 R/W B1RS DVM Ramp Speed BUCK 2 TARGET VOLTAGE 1 REGISTER ...
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BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) 8H'2A Bit 7 Designation Reset Value 0 Note: ** denotes EPROM programmable registers for default value. BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) 8H'2A DEFINITIONS Bit Access Name — — 7:5 Reserved 4:0 ...
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BUCK 3 TARGET VOLTAGE 1 REGISTER (B3TV1) 8H'32 Bit 7 Designation Reserved Reset Value 0 Note: ** denotes EPROM programmable registers for default value. BUCK 3 TARGET VOLTAGE 1 REGISTER (B3TV1) 8H'32 DEFINITIONS Bit Access Name — — 7:5 Reserved ...
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BUCK 3 VOLTAGE RAMP CONTROL REGISTER (B3RC) 8H'34 Bit Designation Reset Value BUCK 3 VOLTAGE RAMP CONTROL REGISTER (B3RC) 8H'34 DEFINITIONS Bit Access Name — — 7:5 Reserved 4:0 R/W B3RC DVM Ramp Speed BUCK FUNCTION REGISTER (BFR) 8H'38 Bit ...
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LDO2–LDO1 VOLTAGE CONTROL REGISTER (L21VCR) 8H'39 Bit 7 Designation LDO 2 Output Voltage (L20V)** Reset Value 1** Note: ** denotes EPROM programmable registers for default value. LDO2–LDO1 VOLTAGE CONTROL REGISTER (L21VCR) 8H'39 DEFINITIONS Bit Access Name 7:4 R/W L2OV 3:0 ...
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LDO4–LDO3 VOLTAGE CONTROL REGISTER (L43VCR) 8H'3A Bit 7 Designation LDO 4 Output Voltage (L4OV)** Reset Value 0** Note: ** denotes EPROM programmable registers for default value. LDO4–LDO3 VOLTAGE CONTROL REGISTER (L43VCR) 8H'3A DEFINITIONS Bit Access Name 7:4 R/W L4OV 3:0 ...
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V _LDO5 VOLTAGE CONTROL REGISTER (L5VCR) 8H'3B CC Bit 7 Designation Reserved Reset Value 0 Note: ** denotes EPROM programmable registers for default value. V _LDO5 VOLTAGE CONTROL REGISTER (L5VCR) 8H'3B DEFINITIONS CC Bit Access Name — — 7:5 Reserved ...
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DIGITAL INTERFACE CONTROL SIGNALS Signal SYS_EN High Voltage Power Enable PWR_EN Low Voltage Power Enable SCL Serial Bus Clock Line SDA Serial Bus Data Line nRSTI Forces an Unconditional Hardware Reset nRSTO Forces an Unconditional Hardware Reset nBATT_FLT Main Battery ...
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WAKEUP register bits Reason for WAKEUP WUP0 SPARE WUP1 TEST_JIG WUP2 PWR_ON short pulse WUP3 PWR_ON long pulse TSD_EW TSD Early Warning INTERNAL THERMAL SHUTDOWN PROCEDURE Thermal shutdown is build to generate early warning (typ. 125°C) which triggers the EXT_WAKEUP ...
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THERMAL MANAGEMENT Application: There is a mode wherein all 6 comparators (flags) can be turned on via the “enallflags” control register bit. This mode allows the user to interrogate the device or system temperature under the set operating conditions. Thus, ...
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Application Note - LP3971 Reset Sequence INITIAL COLD START POWER ON SEQUENCE 1. The Back up battery is connected to the PMU, power is applied to the back-up battery pin, the RTC_LDO turns on and supplies a stable output voltage ...
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POWER-ON TIMING Symbol Description t1 Delay from V _RTC assertion to nRSTO de-assertion CC t2 Delay from nBATT_FLT de-assertion to nRSTI assertion t3 Delay from nRST de-assertion to SYS_EN assertion t4 Delay from SYS_EN assertion to PWR_EN assertion t5 Delay ...
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Application Hints LDO CONSIDERATIONS External Capacitors The LP3971’s regulators require external capacitors for reg- ulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input ...
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BUCK CONSIDERATIONS Inductor Selection There are two main considerations when choosing an induc- tor; the inductor should not saturate, and the inductor current ripple is small enough to achieve the desired output voltage ripple. Different saturation current rating specs are ...
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TABLE 2. Suggested Capacitor and Their Suppliers Model GRM21BR60J106K Ceramic, X5R JMK212BJ106K Ceramic, X5R C2012X5R0J106K Ceramic, X5R Buck Output Ripple Management If V and I increase, the output ripple associated with the IN LOAD Buck Regulators also increases. The figure ...
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Board Layout Considerations PC board layout is an important part of DC-DC converter de- sign. Poor board layout can disrupt the performance of a DC- DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss ...
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Physical Dimensions inches (millimeters) unless otherwise noted 40-Pin Leadless Leadframe Package NS Package Number SQF40A 49 www.national.com ...
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