LTC4255CG#TRPBF Linear Technology, LTC4255CG#TRPBF Datasheet - Page 14

• Manufacturer Part Number: LTC4255CG#TRPBF
• Description: IC NETWORK POWER CTRLR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC4255CG#TRPBF

• Applications: Network Power Controller
• Voltage - Supply: 10.8 V ~ 13.2 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

LTC4255
APPLICATIO S I FOR ATIO
If the autoretry enable bit (B1) is set, then the channel will
automatically restart after the retry delay timer expires
(Figure 12, point E). If the channel successfully powers up
after an autoretry, the Power_OK bit (CO) will be set.
However, FAULT will continue to pull down and the short-
circuit bit (DO) will remain high until the fault is cleared by
setting the FAULT clear bit (BO).
In the case of a short-circuit occuring after a normal
power-up, high rates of change of current (high di/dt)
through the inductance of the cable or even the traces on
the PCB can cause the voltages at OUT1-4 to overshoot.
A 100k resistor should be placed between the drains of
the FETs and the OUT1-4 pins to limit the energy absorbed
by the LTC4255 if the drains of the FETs exceed OUT1-4’s
absolute maximum voltage rating. Also, if the FETs are
not capable of safely absorbing this energy, high-speed
14
SHORT-CIRCUIT STATUS
OPEN-CIRCUIT STATUS
POWER_OK
CURRENT
U
RELAY1
Figure 12. Power-Up Sequence with Shorted Load on Channel 1 with Autoretry Enabled
FAULT
GATE1
OUT1
(D0)
(D4)
(C0)
SDA
SCL
FET
U
AO
ACK
W
TURNS ON
A
FET
t
OD
B
STOP BIT
U
C
t
CL
D
Schottky diodes should be added between the drains of
the FETs and AGND using a layout that minimizes the
trace lengths between the parts.
Address Selection
The lower 5 bits of the serial interface address can be set
by the address selection pins AD0 to AD4 with AD0 being
the least significant bit. The upper two bits are preset to
AD5 = high and AD6 = low. To force an address bit to low,
the address selection pin should be connected to DGND.
To force an address bit to high, the address selection pin
can be left floating and an internal pull-up resistor will pull
the pin up to the internal digital supply voltage (typically
5V). If more noise immunity is needed, the pin can be
connected directly to a 5V or 3.3V external supply.
CL TIMER
EXPIRES
t
R
BO
E
F
ACK
AUTO-RESTART
INITIATED
G
STOP BIT
H
FAULT CLEARED
CL TIMER
EXPIRES
4255 F12
4255f