LTC3447EDD Linear Technology, LTC3447EDD Datasheet - Page 13
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LTC3447EDD
Manufacturer Part Number
LTC3447EDD
Description
IC CONV DC/DC SYNC BUCK 10DFN
Manufacturer
Linear Technology
Type
Step-Down (Buck)r
Datasheet
1.LTC3447EDDPBF.pdf
(16 pages)
Specifications of LTC3447EDD
Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.69 ~ 2.05 V
Current - Output
600mA
Frequency - Switching
1MHz
Voltage - Input
2.5 ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-DFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
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APPLICATIO S I FOR ATIO
The V
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V
of V
continuous mode, I
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
pronounced at higher supply voltages.
I
switches, R
mode, the average output current fl owing through inductor
L is “chopped” between the main switch and the synchro-
nous switch. Thus, the series resistance looking into the
SW pin is a function of both top and bottom MOSFET
R
The R
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
loss dominates the effi ciency loss at medium to high
load currents. In a typical effi ciency plot, the effi ciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 8.
2
DS(ON)
R losses are calculated from the resistances of the internal
R
IN
SW
IN
DS(ON)
that is typically larger than the DC bias current. In
IN
quiescent current is due to two components: the
= (R
and the duty cycle (DC) as follows:
to ground. The resulting dQ/dt is the current out
0.001
0.01
0.1
SW
Figure 8. Power Loss vs Load Current
DS(ON)TOP
1
for both the top and bottom MOSFETs can
0.1
, and external inductor R
IN
DAC = MAX
U
GATECHG
and thus their effects will be more
1
)(DC) + (R
LOAD CURRENT (mA)
2
U
R losses, simply add R
DAC = MIN
10
= f(QT + QB) where QT and
DS(ON)BOT
W
100
L
3447 F08
. In continuous
)(1 – DC)
1000
U
SW
to
R
output current.
Other losses including C
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (ΔI
resistance of C
charge C
The regulator loop then acts to return V
state value. During this recovery time V
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral-
lel with C
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately (25
• C
require a 250µs rise time, limiting the charging current
to about 130mA.
Thermal Considerations
In most applications the LTC3447 does not dissipate much
heat due to its high effi ciency. But, in applications where the
LTC3447 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
To avoid the LTC3447 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
L
LOAD
and multiply the result by the square of the average
). Thus, a 10µF capacitor charging to 3.3V would
OUT
OUT
LOAD
, which generates a feedback error signal.
, causing a rapid drop in V
OUT
• ESR), where ESR is the effective series
. ΔI
OUT
LOAD
IN
immediately shifts by an amount
and C
also begins to charge or dis-
OUT
ESR dissipative losses
LTC3447
OUT
OUT
OUT
. No regulator
can be moni-
to its steady
13
3447f