ADP3290JCPZ-RL ON Semiconductor, ADP3290JCPZ-RL Datasheet - Page 9

• Manufacturer Part Number: ADP3290JCPZ-RL
• Description: IC CTLR BUCK SW REG 40-LFCSP
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of ADP3290JCPZ-RL

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 4
• Voltage - Output: 0.5 ~ 1.6 V
• Frequency - Switching: 250kHz ~ 4MHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Output Voltage: 0.5 V to 1.6 V
• Output Current: 500 uA
• Input Voltage: - 0.3 V to + 6.3 V
• Supply Current: 25 mA
• Switching Frequency: 450 kHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Theory of Operation
PWM control with multiphase logic outputs for use in 2−, 3−,
or 4−phase synchronous buck CPU core supply power
converters. The internal VID DAC is designed to interface with
Intel 8−bit VRD/VRM 11.1 and compatible CPUs. Multiphase
operation is important for producing the high currents and low
voltages demanded by today’s microprocessors. Handling the
high currents in a single−phase converter places high thermal
demands on the components in the system, such as the
inductors and MOSFETs.
high performance topology for the following:
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Startup Sequence
shown in Figure 5. After both the EN and UVLO conditions
are met, the DELAY pin goes through one cycle (TD1).
After this cycle, the internal oscillator is enabled. The first
four clock cycles are blanked from the PWM outputs and
used for phase detection as explained in the Phase Detection
Sequence section. Then, the soft−start ramp is enabled
(TD2), and the output comes up to the boot voltage of 1.1 V.
The boot hold time is determined by the DELAY pin as
it goes through a third cycle (TD3). During TD3, the
processor VID pins settle to the required VID code. When
TD3 is over, the ADP3290 reads the VID inputs and
soft−starts either up or down to the final VID voltage
(TD4).When TD4 and the PWRGD masking time (equal to
VID OTF masking) is completed, a third ramp on the
DELAY pin sets the PWRGD blanking (TD5).
The ADP3290 combines a multi−mode, fixed frequency
The multi−mode control of the ADP3290 ensures a stable,
The ADP3290 follows the VR11.1 startup sequence
Balancing currents and thermals between phases for
both static and dynamic operation
High speed response at the lowest possible switching
frequency and output decoupling
FEPWM and TRDET functions for improved load step
and load release transient response
Minimizing thermal switching losses by using lower
frequency operation
Tight load line regulation and accuracy
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in operation for tailoring design to low cost
or high performance
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Phase Detection Sequence
phase relationship is determined by the internal circuitry
monitoring the PWM outputs. Normally, the ADP3290
operates as a 4−phase PWM controller. Connecting
PWM4 pin to V
2−phase operation, connect PWM4 and PWM3 pins to V
pins sink approximately 100 mA. An internal comparator
checks the voltage of each pin versus a threshold of 3.15 V.
If the pin is tied to V
Otherwise, an internal current sink pulls the pin to GND,
which is below the threshold. PWM1 and PWM2 are low
during the phase detection interval that occurs during the
first four clock cycles of the internal oscillator. After this
time, if the remaining PWM outputs are not pulled to V
the 100 mA current sink is removed, and they function as
normal PWM outputs. If they are pulled to V
current source is removed, and the outputs are driven into a
high impedance state.
driving fast response external gate drivers such as the
ADP3121 and
independently, operation approaching 100% duty cycle is
possible. In addition, more than one PWM output can be on
at the same time to allow overlapping phases.
(ADP3290 PWRGD)
During startup, the number of operational phases and their
Prior to soft−start, while EN is low, the PWM3 and PWM4
The PWM outputs are logic−level devices intended for
(ADP3290 EN)
VID INPUTS
VCC_CORE
VR READY
SUPPLY
VTT I/O
DELAY
CPU
Figure 5. System Startup Sequence
12V
SS
ADP3122.
CC
UVLO
THRESHOLD
CC
programs a 3−phase operation. For
VID INVALID
0.8V
, its voltage is above the threshold.
TD1
Because each phase is monitored
1.0V
TD2
V
(1.7V)
DELAY(TH)
50ms
V
V
(1.1V)
(1.1V)
BOOT
TD3
BOOT
CC
V
V
VID VALID
VID
VID
, the 100 mA
TD5
TD4
CC
CC
.
,