KSZ8995M Micrel Inc, KSZ8995M Datasheet - Page 28
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KSZ8995M
Manufacturer Part Number
KSZ8995M
Description
IC SWITCH 10/100 5PORT 128PQFP
Manufacturer
Micrel Inc
Specifications of KSZ8995M
Applications
*
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Number Of Primary Switch Ports
5
Internal Memory Buffer Size
64
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII/SNI
Power Supply Type
Analog/Digital
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.9/2.6/3.6V
Operating Supply Voltage (min)
1.7/2.4/3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1607 - BOARD EVAL EXPERIMENT KSZ8995MA
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1038
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8995M
Manufacturer:
KENDIN
Quantity:
331
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Manufacturer:
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Quantity:
20 000
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Manufacturer:
MICREL
Quantity:
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Manufacturer:
MICREL
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18
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Manufacturer:
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Company:
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
TI
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Manufacturer:
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Quantity:
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KS8995M
The MII-P5 interface operates in PHY mode only, while the MII-SW interface operates in either MAC mode or PHY mode. These
interfaces are nibble wide data interfaces and therefore run at 1/4 the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators
that convey when the data is valid and without physical layer errors. For half-duplex operation there is a signal that indicates
a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER is not
provided on the MII-SW interface for MAC mode operation. Normally MRXER would indicate a receive error coming from the
physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this
configuration. For PHY mode operation, if the device interfacing with the KS8995M has an MRXER pin, it should be tied low.
For MAC mode operation, if the device interfacing with the KS8995M has an MTXER pin, it should be tied low.
SNI Interface Operation
The SNI (Serial Network Interface) is compatible with some controllers used for network layer protocol processing. This
interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmission
and the other for reception. The signals involved are described in Table 3.
This interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An additional signal on the
transmit side indicates when data is valid. Likewise, the receive side has an indicator that conveys when the data is valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
Advanced Functionality
Spanning Tree Support
To support spanning tree, port 5 is the designated port for the processor.
The other ports (port 1 - port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive enable”
and “learning disable” register settings in Registers 18, 34, 50, and 66 for ports 1, 2, 3 and 4, respectively. The following
description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: the processor should not send any packets to the port. The switch may still send specific packets to the
processor (packets that match some entries in the static table with “overriding bit” set) and the processor should discard those
packets. Note: processor is connected to port 5 via MII interface. Address learning is disabled on the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: the processor should not send any packets to the port(s) in this state. The processor should program the static
table with the entries that it needs to receive (e.g. BPDU packets). The “overriding” bit should also be set so that the switch
will forward those specific packets to the processor. Address learning is disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The processor
may send packets to the port(s) in this state, see “Special Tagging Mode” section for details. Address learning is disabled on
the port in this state.
M9999-062309
SNI Signal
TXEN
TXD
TXC
COL
CRS
RXD
RXC
Description
Transmit enable
Serial transmit data
Transmit clock
Collision detection
Carrier sense
Serial receive data
Receive clock
Table 3. SNI Signals
28
KS8995M Signal
SMTXEN
SMTXD[0]
SMTXC
SCOL
SMRXDV
SMRXD[0]
SMRXC
Micrel, Inc.
June 2009