ADUM1402ARWZ Analog Devices Inc, ADUM1402ARWZ Datasheet - Page 5

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ADUM1402ARWZ

Manufacturer Part Number
ADUM1402ARWZ
Description
IC DIGITAL ISOLATOR 4CH 16-SOIC
Manufacturer
Analog Devices Inc
Series
iCoupler®r
Datasheet

Specifications of ADUM1402ARWZ

Propagation Delay
100ns
Inputs - Side 1/side 2
2/2
Number Of Channels
4
Isolation Rating
2500Vrms
Voltage - Supply
2.7 V ~ 5.5 V
Data Rate
1Mbps
Output Type
Logic
Package / Case
16-SOIC (0.300", 7.5mm Width)
Operating Temperature
-40°C ~ 105°C
No. Of Channels
4
Supply Current
1.5mA
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
SOIC
No. Of Pins
16
Operating Temperature Range
-40°C To +105°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUM1402EBA - KIT DEV W/BOARD ADUM1402 1MBPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Parameter
1
2
3
4
5
6
7
8
9
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See
on per-channel supply current for unloaded and loaded conditions. See the
for a given data rate.
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the
See F
Figure 15
within the recommended operating conditions.
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
PHL
PSK
ADuM140xBRW
ADuM140xCRW
For All Models
H
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching, Codirectional
Channel-to-Channel Matching, Opposing-
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching, Codirectional
Channel-to-Channel Matching, Opposing-
Output Disable Propagation Delay (High/Low
Output Enable Propagation Delay (High
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
Common-Mode Transient Immunity at Logic
Refresh Rate
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
igure 8
Change vs. Temperature
Change vs. Temperature
Change vs. Temperature
Channels
Directional Channels
Channels
Directional Channels
to High Impedance)
Impedance to High/Low
High Output
Low Output
for total V
through F
7
7
DD1
8
8
igure 10
and V
5
5
4
4
DD2
3
3
7
7
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See F
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
6
6
6
PLH
PLH
PLH
− t
− t
− t
PHL
7
PHL
PHL
|
|
|
O
5
5
5
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
PHL
9
or t
9
Ix
signal to the 50% level of the rising edge of the V
PLH
Symbol
PWD
t
t
PW
t
PWD
t
t
t
PW
t
PWD
t
t
t
t
t
t
|CM
|CM
f
I
I
r
DDI (D)
DDO (D)
PSK
PSKCD
PHL
PSK
PSKCD
PSKOD
PHL
PSK
PSKCD
PSKOD
PHZ
PZH
R
that is measured between units at the same operating temperature, supply voltages, and output load
/t
, t
, t
F
, t
, t
H
L
|
/t
|
PLH
PLH
PLH
PZL
PSKOD
Rev. G | Page 5 of 32
Power Consumption
Min
10
20
90
18
25
25
Ix
signal to the 50% level of the falling edge of the V
O
section for guidance on calculating the per-channel supply current
> 0.8 V
Typ
11
32
5
8.3
120
27
0.5
3
6
6
2.5
35
35
1.2
0.19
0.05
ADuM1400/ADuM1401/ADuM1402
DD2
Ox
. CM
Max Unit
40
50
50
100
50
3
15
3
6
11.1 ns
32
2
10
2
5
8
8
signal.
L
is the maximum common-mode voltage slew rate
mA/Mbps
mA/Mbps
ns
ps/°C
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
Figure 8
Test Conditions
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Ix
Ix
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
through
= V
= 0 V, V
Ox
Power Consumption
signal. t
DD1
or V
CM
Figure 10
PLH
= 1000 V,
DD2
propagation delay is
igure 11
, V
CM
for information
= 1000 V,
through
section.

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