HCPL-063N#500 Avago Technologies US Inc., HCPL-063N#500 Datasheet - Page 16
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HCPL-063N#500
Manufacturer Part Number
HCPL-063N#500
Description
OPTOCOUPLER 2CH 10MBD 8-SOIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.HCPL-061A-000E.pdf
(17 pages)
Specifications of HCPL-063N#500
Package / Case
8-SOIC (0.154", 3.90mm Width)
Voltage - Isolation
3750Vrms
Number Of Channels
1, Unidirectional
Current - Output / Channel
50mA
Data Rate
10MBd
Propagation Delay High - Low @ If
53ns @ 3.5mA
Current - Dc Forward (if)
10mA
Input Type
DC
Output Type
Open Collector
Mounting Type
Surface Mount
Isolation Voltage
3750 Vrms
Maximum Continuous Output Current
50 mA
Maximum Fall Time
12 ns
Maximum Forward Diode Current
10 mA
Maximum Rise Time
42 ns
Minimum Forward Diode Voltage
1 V
Output Device
Logic Gate Photo IC
Configuration
2 Channel
Maximum Baud Rate
10 MBps
Maximum Forward Diode Voltage
1.6 V
Maximum Reverse Diode Voltage
3 V
Maximum Power Dissipation
60 mW
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Elements
2
Baud Rate
10Mbps
Forward Voltage
1.6V
Forward Current
10mA
Output Current
50mA
Package Type
SOIC
Operating Temp Range
-40C to 85C
Power Dissipation
60mW
Propagation Delay Time
100ns
Pin Count
8
Mounting
Surface Mount
Reverse Breakdown Voltage
3V
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
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Figure 23. TTL open-collector/open drain gate drive circuit for
HCPL-261A/-261N families.
OPEN-COLLECTOR/
Table 1. Effects of Common Mode Pulse Direction on Transient I
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (t
amount of time required for an input signal to propa-
gate to the output, causing the output to change from
low to high. Similarly, the propagation delay from high
to low (t
signal to propagate to the output, causing the output to
change from high to low (see Figure 9).
Pulse-width distortion (PWD) results when t
differ in value. PWD is defined as the difference between
t
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typi-
cally, PWD on the order of 20-30% of the minimum pulse
width is tolerable; the exact figure depends on the par-
ticular application (RS232, RS422, T-1, etc.).
Propagation delay skew, t
to consider in parallel data applications where synchro-
PLH
If dV
positive (>0)
negative (<0)
and t
LOGIC GATE)
OPEN-DRAIN
CM
/dt Is:
PHL
(OR ANY
V
74HC00
PHL
CC
) is the amount of time required for the input
and often determines the maximum data
then I
away from LED
anode through C
toward LED
anode through C
HCPL- 261A fig 22
PSK
LP
Flows:
, is an important parameter
820 Ω
LA
LA
1
2
3
4
HCPL-261X
PLH
and I
away from LED
cathode through C
toward LED
cathode through C
PLH
and t
) is the
LN
LED
Flows:
LED
PHL
OUTPUT LOGIC
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocou-
plers.
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
either t
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and op-
erating temperature). As illustrated in Figure 25, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, t
the shortest propagation delay, either t
longest propagation delay, either t
As mentioned earlier, t
parallel data transmission rate. Figure 26 is the timing
diagram of a typical parallel data application with both
the clock and the data lines being sent through opto-
couplers.
Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families.
TOTEM-POLE
LC
LC
(OR ANY
74HC04
GATE)
PLH
or t
V
PHL
Is Momentarily:
CC
LED I
decreased
If |I
increased
, for any given group of optocouplers
LP
F
| < |I
HCPL- 261A fig 23
Current
PSK
LN
1N4148
|,
750 Ω
can determine the maximum
PSK
is the difference between
PLH
1
2
3
4
or t
Is Momentarily:
LED I
PLH
If |I
decreased
increased
HCPL-261A/261N
PHL
or t
LP
F
.
| > |I
Current
PHL
LED
LN
, and the
|,