MA240017 Microchip Technology, MA240017 Datasheet - Page 107
MA240017
Manufacturer Part Number
MA240017
Description
MODULE PLUG-IN PIC24F16KA102 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of MA240017
Accessory Type
Plug-In Module (PIM) - PIC24F16KA102
Product
Microcontroller Modules
Data Bus Width
16 bit
Core Processor
PIC24F16KA102
Operating Supply Voltage
3 V to 3.6 V
Development Tools By Supplier
Integrated Development Environment, Assembler, ANSI C Compiler
Processor Series
PIC24F
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC24
Silicon Core Number
PIC24F
Silicon Family Name
PIC24FxxKAxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Explorer 16 (DM240001 or DM240002)
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MA240017
Manufacturer:
MICROCHIP
Quantity:
12 000
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REGISTER 10-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0
DSEN
U-0
—
2:
All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
(2)
Preliminary
—
—
PIC24F16KA102 FAMILY
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(1)
U-0
U-0
—
—
x = Bit is unknown
DSBOR
R/W-0
U-0
—
(2)
DS39927B-page 105
RELEASE
R/C-0, HS
U-0
—
bit 8
bit 0
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