Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 108

ADAPTER ICE Z8 ENCORE 64K 64LQFP

Z8F64220100ZDA

Manufacturer Part Number
Z8F64220100ZDA
Description
ADAPTER ICE Z8 ENCORE 64K 64LQFP
Manufacturer
Zilog
Datasheets

Specifications of Z8F64220100ZDA

Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3403
Table 47. Watchdog Timer Approximate Time-Out Delays
PS019921-0308
WDT Reload Value
FFFFFF
000004
Watchdog Timer Refresh
Watchdog Timer Time-Out Response
(Hex)
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer then counts down to
instruction is executed by the eZ8
downcounter to be reloaded with the WDT Reload value stored in the Watchdog Timer
Reload registers. Counting resumes following the reload operation.
When the Z8 Encore! XP
(through the On-Chip Debugger), the Watchdog Timer is continuously refreshed to pre-
vent spurious Watchdog Timer time-outs.
The Watchdog Timer times out when the counter reaches
Watchdog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit
determines the time-out response of the Watchdog Timer. For information on
programming of the WDT_RES Option Bit, see
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of
counter is not automatically returned to its Reload Value.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP
F64XX Series devices are in STOP mode, the Watchdog Timer automatically initiates a
Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the
STOP bit in the Watchdog Timer Control register are set to 1 following WDT time-out in
WDT Reload Value
16,777,215
(Decimal)
4
®
F64XX Series devices are operating in DEBUG Mode
FFFFFH
(with 10 kHz typical WDT oscillator frequency)
CPU. Execution of the WDT instruction causes the
and continues counting. The Watchdog Timer
1677.5 s
Typical
400 µs
Approximate Time-Out Delay
Option Bits
Z8 Encore! XP
000000H
on page 191.
000000H
Description
Maximum time-out delay
Product Specification
Minimum time-out delay
. A time-out of the
unless a WDT
®
F64XX Series
Watchdog Timer
94

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