Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 128

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

Table 57. UART Control 1 Register (UxCTL1)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
MPMD[1]
7
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is over-
ridden by the
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
MPEN
6
MPEN
MPMD[0]
bit.
5
MPBT
F43H and F4BH
4
R/W
0
DEPOL
3
BRGCTL
Z8 Encore! XP
2
Product Specification
RDAIRQ
1
®
F64XX Series
IREN
0
UART
114