Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 142

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

PS019921-0308
SPI Clock Phase and Polarity Control
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see NUMBITS field in the
page 136). In both Master and Slave SPI devices, data is shifted on one edge of the SCK
and is sampled on the opposite edge where data is stable. Edge polarity is determined by
the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. Other GPIO output pins can also be employed to select exter-
nal SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin must
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error Flag is set in the
SPI Status register.
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active Low
clock and has no effect on the transfer format.
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-
tally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
Table 62. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit
Falling
Falling
Rising
Rising
Edge
Table 62
SCK Receive
Z8 Encore! XP
lists the SPI Clock Phase and
Falling
Falling
Rising
Rising
Edge
Product Specification
SPI Mode Register
Serial Peripheral Interface
®
F64XX Series
SCK Idle
State
High
High
Low
Low
on
128