Z8F64220100ZDA Zilog, Z8F64220100ZDA Datasheet - Page 163

• Manufacturer Part Number: Z8F64220100ZDA
• Description: ADAPTER ICE Z8 ENCORE 64K 64LQFP
• Manufacturer: Zilog

Specifications of Z8F64220100ZDA

• Module/board Type: *
• For Use With/related Products: Z8 Encore!™
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3403

PS019921-0308
Read Transaction with a 7-Bit Address
Figure 31. Receive Data Transfer Format for a 7-Bit Addressed Slave
16. If the I
17. The I
18. If more bytes remain to be sent, return to
19. If the last byte is currently being sent, software sets the STOP bit of the I
20. The I
21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
22. The I
Figure 31
The shaded regions indicate data transferred from the I
unshaded regions indicate data transferred from the slaves to the I
Follow the steps below for a read operation to a 7-bit addressed slave:
1. Software writes the I
2. Software asserts the START bit of the I
3. If this is a single byte transfer, Software asserts the NAK bit of the I
S
high period of SCL, the I
Continue with
If the slave does not acknowledge the second address byte or one of the data bytes, the
I
Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH
bits and clearing the TXI bit. The I
and clears the STOP and NCKI bits. The transaction is complete (ignore the following
steps).
Transmit interrupt is asserted.
register (or START bit to initiate a new transaction). In the STOP case, software also
clears the TXI bit of the I
the STOP or START bit is already set, the NCKI interrupt does not occur.
the STOP (or START) bit.
so that after the first byte of data has been read by the I
Acknowledge is sent to the I
2
C Controller sets the NCKI bit and clears the ACK bit in the I
2
2
2
C Controller sends the STOP (or RESTART) condition to the I
displays the data transfer format for a read operation to a 7-bit addressed slave.
C Controller shifts the data out by the SDA signal. After the first bit is sent, the
C Controller completes transmission of the last data byte on the SDA signal.
2
Slave Address
C slave sends an acknowledge by pulling the SDA signal low during the next
step
17.
2
C Data register with a 7-bit slave address plus the read bit (=1).
2
2
C Controller sets the ACK bit in the I
C Control register at the same time.
2
C slave.
R = 1
2
C Controller sends the STOP condition on the bus
2
C Control register.
step
A
14.
Data
2
Z8 Encore! XP
C Controller to slaves and
2
C Controller, a Not
A
Product Specification
2
C Controller.
2
2
C Status register.
C Status register.
Data
2
C Control register
®
2
C bus and clears
F64XX Series
2
I2C Controller
C Control
A
P/S
149