ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 92
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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- Download datasheet (6Mb)
7.11
7.11.1
7.11.2
7.11.3
8077H–AVR–12/09
Register Description - DFLL32M/DFLL2M
CTRL - DFLL Control Register
CALA - Calibration Register A
CALB - Calibration Register B
• Bit 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator
CALA and CALB register holds the 13 bit DFLL calibration value that is used for automatic run-
time calibration the internal oscillator. When the DFLL is disabled, the calibration registers can
be written by software for manual run-time calibration of the oscillator. The oscillators will be cal-
ibrated according to the calibration value in these registers also when the DFLL is disabled.
• Bit 7:0 - CALL[7:0]: DFLL Calibration bits
These bits hold the 7 Least Significant Bits (LSB) of the calibration value for the oscillator. After
reset CALL is set to its middle value, and during automatic runtime calibration of the oscillator
these bits are use to change the oscillator frequency. The bits are controlled by the DFLL when
the DFLL is enabled.
• Bit 7:4 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R
7
R
0
7
–
0
R
7
–
0
R
6
R
1
6
–
0
R
6
–
0
R/W
5
–
R
0
5
0
R
5
–
0
R/W
R/W
R
4
0
4
–
0
4
x
CALL[7:0]
R/W
R/W
R
3
0
3
–
0
3
x
CALH[12:8]
R/W
R/W
R
2
–
0
2
0
2
x
R/W
R/W
R
1
–
0
1
0
1
x
XMEGA A
ENABLE
R/W
R/W
R/W
0
0
0
0
0
x
CTRL
CALA
CALB
92
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