OM6290 NXP Semiconductors, OM6290 Datasheet - Page 13
![DEMO BOARD LCD GRAPHIC DRIVER](/photos/9/4/90479/om6290_sml.jpg)
OM6290
Manufacturer Part Number
OM6290
Description
DEMO BOARD LCD GRAPHIC DRIVER
Manufacturer
NXP Semiconductors
Datasheets
1.PCF8576T1118.pdf
(44 pages)
2.OM6290.pdf
(30 pages)
3.OM6290.pdf
(51 pages)
4.OM6290.pdf
(83 pages)
Specifications of OM6290
Main Purpose
Displays, LCD Controller
Embedded
Yes, MCU, 16/32-Bit
Utilized Ic / Part
PCF2119, PCF8531, PCF8576
Primary Attributes
Character, Graphic and Segment LCD Drivers
Secondary Attributes
JTAG, I²C, UART & USB Interfaces
Description/function
Demo Board
Interface Type
USB, I2C, JTAG, UART
Data Bus Width
4 bit, 8 bit, 16 bit
Operating Voltage
1.8 V to 5.5 V
For Use With/related Products
PCF8576DT, PCF2119S, PCF8531
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4703
NXP Semiconductors
PCF8531
Product data sheet
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] In the application, T2 must be left open-circuit.
If the on-chip oscillator is used, this input must be connected to V
If the internal V
If an external V
will be damaged.
If only the internal Power-On Reset (POR) is used, this input must be connected to V
V
V
connected together.
Serial data acknowledge for the I
fully I
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from
the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus
pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be
able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK
output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where
the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to
the system SDA line to guarantee a valid LOW level.
If ENR is connected to V
must be connected to V
In the application, this input must be connected to V
V
DD1
DD3
SS1
2
and V
is for the logic supply, V
must be connected together. If only one supply voltage is available, V
C-bus compatible. Having the acknowledge output separated from the serial data line is
SS2
All information provided in this document is subject to legal disclaimers.
must be connected together.
LCD
LCD
is used in the application, then pin V
generation is used, V
Rev. 05 — 10 August 2010
DD1
SS
, Power-On Reset (POR) is disabled; to enable Power-On Reset (POR) ENR
.
DD2
2
and V
C-bus. By connecting SDACK to SDA externally, the SDA line becomes
DD3
LCDOUT
are for the voltage multiplier. For split power supplies, V
, V
LCDIN
SS
.
LCDOUT
, and V
LCDSENSE
must be left open-circuit, otherwise the chip
DD1
.
34 x 128 pixel matrix driver
must be connected together.
DD1
, V
DD2
PCF8531
© NXP B.V. 2010. All rights reserved.
, and V
DD1
.
DD3
must be
DD2
13 of 51
and