W682510DK Nuvoton Technology Corporation of America, W682510DK Datasheet - Page 4

• Manufacturer Part Number: W682510DK
• Description: KIT DEVELOPMENT FOR W682510
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W682510DK

• Main Purpose: Telecom, CODEC
• Embedded: No
• Utilized Ic / Part: W682510
• Primary Attributes: Dual Voice Band PCM CODEC
• Secondary Attributes: Parallel & Serial Modes, 2 RJ9 Handset Jacks
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION ................................................................................................................. 2
1. GENERAL DESCRIPTION ................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM ............................................................................................................................. 3
4. TABLE OF CONTENTS...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION ............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION ........................................................................................................... 8
8. TIMING DIAGRAMS ......................................................................................................................... 15
9. ABSOLUTE MAXIMUM RATINGS................................................................................................... 19
7.1. Transmit Path
7.2. Receive Path
7.3. Power Signals
7.4. PCM Interface
7.5. Power State Modes
7.1.1. AI1, AI2, AO1-, AO2-.............................................................................................................. 9
7.1.2. PCMT1 ................................................................................................................................... 9
7.1.3. PCMT2 ................................................................................................................................. 10
7.2.1. RO1, RO2 ............................................................................................................................ 10
7.2.2. PCMR1................................................................................................................................. 11
7.2.3. PCMR2................................................................................................................................. 11
7.3.1. V
7.3.2. V
7.3.3. V
7.3.4. V
7.3.5. PUI ....................................................................................................................................... 12
7.4.1. μ/A-Law ................................................................................................................................ 12
7.4.2. BCLK .................................................................................................................................... 13
7.4.3. FSR ...................................................................................................................................... 13
7.4.4. FST....................................................................................................................................... 13
7.4.5. PCMMS ................................................................................................................................ 13
7.5.1. Power Save Mode................................................................................................................ 13
7.5.2. Power Down Mode............................................................................................................... 14
7.5.3. Power Save/Down Output pin state ..................................................................................... 14
DD
SSA
SSD
REF
........................................................................................................................................ 11
...................................................................................................................................... 11
...................................................................................................................................... 11
...................................................................................................................................... 12
............................................................................................................................ 10
............................................................................................................................. 8
.......................................................................................................................... 11
.......................................................................................................................... 12
................................................................................................................. 13
- 4 -
W682510/W682310