STEVAL-CCH002V1 STMicroelectronics, STEVAL-CCH002V1 Datasheet



Manufacturer Part Number

Specifications of STEVAL-CCH002V1

Design Resources
STEVAL-CCH002V1 Gerber Files STEVAL-CCH002V1 Schematic STEVAL-CCH002V1 Bill of Material
Main Purpose
Video, HDMI and Video Switches
Yes, MCU, 8-Bit
Utilized Ic / Part
Primary Attributes
DVI-I, 2 HDMI, Y Pb Pr, S-Video, CVBS, VGA - Input and Output
Secondary Attributes
LCD Displays Selection Status of Video Switches and Buffers
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Table 1.
December 2008
Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
3.4 Gbps data rate per channel
Fully automatic adaptive equalizer
Single supply V
Integrated open-drain I
data channel (DDC)
5.3 V tolerant DDC and HPD I/Os
Lock-up free operation of I
0 to 400 kHz clock frequency for I
Low capacitance of all the channels
Equalizer regenerates the incoming attenu-
ated TMDS signal
Buffer drives the TMDS outputs over long PCB
track lengths
Low output skew and jitter
Tight input thresholds reduce bit error rates
On-chip selectable 50 Ω input termination
Low ground bounce
Data and control inputs provide undershoot
clamp diode
-40°C to 85°C operating temperature range
Evaluation kit is available
Order code
> ±
5 KV HBM for all TMDS I/Os
Device summary
: 3.135 to 3.465 V
Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer
C buffer for display
Operating temperature
C bus
-40°C to 85°C
C bus
Rev 4
The STDVE003A integrates a 4-channel 3.4 Gbps
TMDS equalizer and a 3:1 switch to select one of
the three HDMI ports. The 3-input HDMI ports can
be either external ports or internal sources. High-
speed data paths and flow-through pinout
minimize the internal device jitter and simplify the
board layout. The equalizer overcomes the
intersymbol interference (ISI) jitter effects from
lossy cables. The buffer/driver on the output can
drive the TMDS output signals over long
distances. In addition to this, STDVE003A
integrates the 50 Ω termination resistor on all the
input channels to improve performance and
reduce board space. The device can be placed in
a low-power mode by disabling the output current
drivers. The STDVE003A is ideal for advanced TV
and STB applications supporting HDMI/DVI
standard. The differential signal from the
HDMI/DVI ports can be routed through the
STDVE003A to guarantee good signal quality at
the HDMI receiver. Designed for very low skew,
jitter and low I/O capacitance, the switch
preserves the signal integrity to pass the stringent
HDMI compliance requirements.
Tape and reel

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STEVAL-CCH002V1 Summary of contents

Page 1

Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer Features ■ Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface ■ Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels ■ 340 MHz maximum clock ...

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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STDVE003A List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures List of figures Figure 1. STDVE003A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STDVE003A 1 Block diagram Figure 1. STDVE003A block diagram HDMI input port A HDMI input port B HDMI input port C DDC port A DDC port B DDC port C S1,S2,S3 HPD port A HPD port B HPD port C ...

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Block diagram Figure 3. DDC I A_DDC_SDA B_DDC_SDA C_DDC_SDA A_DDC_SCL B_DDC_SCL C_DDC_SCL S1, S2, S3 1.1 Application diagrams Figure 4. STDVE003A in a digital TV 6/ bus repeater I C bus repeater Switch Game DVD-R console Digital TV ...

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STDVE003A 2 Pin configuration Figure 5. Pin configuration (TQFP80 package) DDC_1_PWR SDA1 REXT EQ_BOOST DDC_Y_PWR Table 2. Pin description Pin number 1 DDC_1_PWR 11 14 ...

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Pin configuration Table 2. Pin description (continued) Pin number DDC_Y_PWR DDC_3_PWR ...

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STDVE003A Table 2. Pin description (continued) Pin number DDC_2_PWR 76, 77 ...

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Functional description 3 Functional description The STDVE003A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standard like TMDS. The device passes the differential inputs from a video source to a common ...

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STDVE003A Figure 6. STDVE003A gain vs. frequency The STDVE003A equalizer is fully adaptive and automatic in function. The default setting of EQ_BOOST = L is recommended for optimal operation. The equalizer’s performance is optimized for all frequencies over the cable ...

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Functional description across the REXT. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 TMDS voltage levels The TMDS interface standard is a signaling method intended ...

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STDVE003A 3.2.1 SEL operating modes The active source is selected by configuring source select inputs, S1, S2 and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I interface of the selected input port ...

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Functional description 2 3 DDC line repeater The device contains two identical bidirectional open-drain, non-inverting buffer circuits that 2 enable I C DDC bus lines to be extended without degradation in system performance. The STDVE003A buffers both the ...

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STDVE003A Table 6. Bias parameter Parameter Bandgap voltage The output voltage swing depends on 3 components: supply voltage (V resistor (R ) and current drive (I T termination resistor can vary from 50 The voltage on the output is given ...

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Maximum rating 4 Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...

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STDVE003A 4.1 Recommended operating conditions 4.2 DC electrical characteristics T = -40 to +85 ° Table 9. Power supply characteristics Symbol Parameter V Supply voltage CC I Supply current CC Table 10. DC specifications for TMDS differential inputs ...

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Maximum rating Table 11. DC specifications for TMDS differential ouputs Symbol Parameter Single-ended high level V OH output voltage Single-ended low level V OL output voltage Single ended output V swing swing voltage Differential output V voltage OD (1) (peak-to-peak) ...

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STDVE003A Table 12. DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs Symbol Parameter V HIGH level input voltage IH V LOW level input voltage IL V Clamp diode voltage IK I Input high current IH I Input low ...

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Maximum rating Table 15. DDC I/O pins (switch) Symbol Parameter I Input leakage current I(leak) C Input/output capacitance I/O 20/42 Test condition Min V = 3.465 ports = 5 port = 0.0 V ...

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STDVE003A Table 16. Status pins (Y_HPD) Symbol Parameter V High level input voltage IH V Low level input voltage IL I Input leakage current I(leak) A_HPD, B_HPD, C_HPD) Table 17. Status pins ( Symbol Parameter V Voltage C Input/output capacitance ...

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Maximum rating 4.3 DC electrical characteristics ( -40 to +85 ° Table 18. Supplies Symbol Parameter V DC supply voltage CC Table 19. Input/output SDA, SCL Symbol Parameter High level input V IH voltage Low level ...

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STDVE003A 4.4 Dynamic switching characteristics T = -40 to +85 ° Typical values are at T Table 20. Clock and data rate Symbol Parameter Clock frequency f (1/10th of the CK differential data rate) D Signaling rate rate ...

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Maximum rating Table 23. Skew times Symbol Parameter Inter-pair channel-to- t SK(O) channel output skew t Pulse skew SK(P) Intra-pair differential t SK(D) skew Output channel to t SK(CC) channel skew Table 24. Turn-on and turn-off times Symbol Parameter TMDS ...

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STDVE003A Table 27. Jitter Symbol Parameter (1) t Total jitter JIT 1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = V parameter is not production-tested ...

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Maximum rating 4.5 Dynamic switching characteristics ( -40 to +85 ° Typical values are (1) Table 28 repeater Symbol Parameter clock frequency SCL t Low duration on ...

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STDVE003A 2 (1) Table 28 repeater (continued) Symbol Parameter t High duration on SCL pin HIGH t High duration on SCL pin HIGH Test condition 100 KHz See Figure 19 Voltage on line = 5 V Cmax = ...

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Maximum rating 2 (1) Table 28 repeater (continued) Symbol Parameter t Propagation delay PHL Output fall time t f 28/42 Test condition 400 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, ...

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STDVE003A 2 (1) Table 28 repeater (continued) Symbol Parameter t Output fall time f t Output rise time r t Output rise time r 1. All the timing values are tested during characterization and are guaranteed by design ...

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Maximum rating Figure 7. Test circuit for electrical characteristics load capacitance: include jig and probe capacitance termination resistance; should be equal Figure 8. TMDS output driver TMDS driver 1. Z ...

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STDVE003A Figure 9. Test circuit for HDMI receiver and driver Ω TMDS TMDS receiver driver = ...

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Maximum rating Figure 10. Test circuit for turn off and turn off times 1.15 V 1.0 V 1.15 V 1.0 V Pulse generator Figure 11. Test circuit for short circuit output current 32/42 V ...

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STDVE003A Figure 12. Propagation delays VA VCM Output Figure 13. Turn-on and turn-off times VCM V ID(p-p) V OD(O) tpLH 80% V OD(p-p) 20% tr SHDN_N 1. OFF V when V ...

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Maximum rating Figure 14. TSK(O) Data In Data Out at Port 0 Data Out at Port 1 Figure 15. TSK(P) Figure 16. TSK(D) 34/42 tpLHX tpHLX 2.5V tpLHY tSK( tpLHy – tpLHx | or | tpHLy – tpHLx ...

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STDVE003A Figure 17. AC waveform 1 (I Figure 18. Test circuit for AC measurements (I 2 Figure 19 bus timing 2 C lines lines) Maximum rating 35/42 ...

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Application information 5 Application information 5.1 Power supply sequencing Proper power-supply sequencing is advised for all CMOS devices recommended to always apply V CC 5.2 Power supply requirements Bypass each of the V device as possible, with the ...

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STDVE003A 2 5.3 lines application information A typical application is shown in the figure below. In the example, the system master is running 100 kHz unless the slave bus is isolated and then ...

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Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and ...

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STDVE003A Table 30. TQFP80 mechanical data Symbol ccc Figure 22. TQFP80 tape information Millimeters Min Typ 0.050 0.950 1.000 0.170 0.220 0.090 14.000 12.000 9.500 ...

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Package mechanical data Figure 23. Reel information Table 31. Reel mechanical data (dimensions in mm) A 330.2 40/ ± 13 0.25 178 STDVE003A 0084694_J T 24.4 ...

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STDVE003A 7 Revision history Table 32. Document revision history Date 23-Apr-2008 26-May-2008 21-Jul-2008 01-Dec-2008 Revision 1 Initial release. 2 Minor updates: Table 4,Table Added: Fully automatic adaptive equalizer feature 3 Modified: title, features Removed: Table 21.: Equalizer gain Updated ESD ...

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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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