KIT33887EKEVBE Freescale Semiconductor, KIT33887EKEVBE Datasheet - Page 8
![BOARD EVALUATION FOR MC33887](/photos/37/57/375700/kit33887ekevbe_bd_sml.jpg)
KIT33887EKEVBE
Manufacturer Part Number
KIT33887EKEVBE
Description
BOARD EVALUATION FOR MC33887
Manufacturer
Freescale Semiconductor
Type
Charge Pumpsr
Specifications of KIT33887EKEVBE
Main Purpose
Power Management, H Bridge Driver (Internal FET)
Embedded
No
Utilized Ic / Part
MC33887
Primary Attributes
5A, 5 ~ 28V, PWM to 20kHz, Active Current Limit
Secondary Attributes
Fault Status, Sleep Mode, Proportional Current Mirror Output
Input Voltage
8 V to 20 V
Board Size
50.8 mm x 50.8 mm
Maximum Operating Temperature
+ 85 C
Product
Power Management Modules
Dimensions
50.8 mm x 50.8 mm
Silicon Manufacturer
Freescale
Silicon Core Number
MC33887
Kit Application Type
Power Management - Motor Control
Application Sub Type
DC Brushed Motor
Kit Contents
Board, CD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
MC33887
8
33887
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS
Notes
Junction-to-Board (Bottom Exposed Pad Soldered to Board)
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s)
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)
(14)
Junction-to-Case (Exposed Pad)
10
11
12
13
14
15
9
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
HSOP (6.0 W)
PQFN (4.0 W)
SOICW-EP (2.0 W)
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual R
values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die
temperature represents ~ 16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R
less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Indicates the maximum thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Rating
(15)
(13)
(9)
,
(10)
Symbol
R
R
R
R
,
θ
(11)
θ
θ
θ
JMA
JB
JA
JC
,
(12)
Analog Integrated Circuit Device Data
Value
~ 0.8
~7.0
~8.0
~9.0
~1.2
~2.0
~ 41
~ 50
~ 62
~ 18
~ 21
~ 23
Freescale Semiconductor
θ
JB
(junction-to-PC board)
θ
JC
-total must be
°C/W
°C/W
°C/W
°C/W
Unit