EVAL-AD7739EBZ Analog Devices Inc, EVAL-AD7739EBZ Datasheet - Page 27

• Manufacturer Part Number: EVAL-AD7739EBZ
• Description: BOARD EVAL FOR AD7739
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7739EBZ

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 15.1k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 85mW @ 5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD7739
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MULTIPLEXER, CONVERSION, AND DATA
OUTPUT TIMING
The specified conversion time includes one or two settling and
sampling periods and a scaling time.
With chopping enabled (Figure 24), a conversion cycle starts
with a settling time of 43 MCLK cycles or 44 MCLK cycles
(~7 µs with a 6.144 MHz MCLK) to allow the circuits following
the multiplexer to settle. The sigma-delta modulator then
samples the analog signals and the digital filter processes the
digital data stream. The sampling time depends on FW, i.e., on
the channel conversion time register contents. After another
settling of 42 MCLK cycles (~6.8 µs), the sampling time is
repeated with a reversed (chopped) analog input signal. Then,
during the scaling time of 163 MCLK cycles (~26.5 µs), the two
results from the digital filter are averaged, scaled using the
calibration registers, and written into the channel data register.
Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
Figure 24. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
– CHANNEL 0
MULTIPLEXER
RDY
SETTLING
MULTIPLEXER
RDY
TIME
CHANNEL 0
+ CHANNEL 1
SETTLING
SAMPLING
TIME
TIME
CONVERSION TIME
Rev. 0 | Page 27 of 32
CONVERSION TIME
SAMPLING
SETTLING
CHANNEL 1
TIME
TIME
With chopping disabled (Figure 25), only one sampling time is
preceded by a settling time of 43 MCLK or 44 MCLK cycles and
followed by a scaling time of 163 MCLK cycles.
The RDY pin goes high during the scaling time, regardless of its
previous state. The relevant RDY bit is set in the ADC status
register and in the channel status register, and the RDY pin goes
low when the channel data register is updated and the channel
conversion cycle is finished. If in continuous conversion mode,
the part will automatically continue with a conversion cycle on
the next enabled channel.
Note that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and
effective per channel data rates depend on all enabled
channel settings.
SAMPLING
– CHANNEL 1
SCALING
TIME
TIME
SCALING
TIME
03742-0-025
03742-0-024
AD7739