STEVAL-PSQ001V1 STMicroelectronics, STEVAL-PSQ001V1 Datasheet - Page 37

• Manufacturer Part Number: STEVAL-PSQ001V1
• Description: BOARD EVAL BASED ON PM6680A
• Manufacturer: STMicroelectronics
• Type: Other Power Managementr

Specifications of STEVAL-PSQ001V1

• Design Resources: STEVAL-PSQ001V1 Gerber Files STEVAL-PSQ001V1 Schematic STEVAL-PSQ001V1 Bill of Material
• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 6, Non-Isolated
• Voltage - Output: 0.9 ~ 2.5 V, 1 ~ 3.3 V, 2x 3.3 V, 2.5 V, 5 V
• Current - Output: 4A, 2A, 800mA, 400mA, 400mA, 150mA
• Voltage - Input: 5 ~ 36V
• Regulator Topology: Buck
• Frequency - Switching: 200kHz, 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: PM6680A
• Input Voltage: 5 V to 36 V
• Output Voltage: 1 V to 3.3 V
• Product: Power Management Modules
• Silicon Manufacturer: ST Micro
• Silicon Core Number: PM6680A
• Kit Application Type: Power Management
• Application Sub Type: Power Supply
• Kit Contents: Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: PM6680A
• Other names: 497-6425; STEVAL-PSQ001V1

PM6680A
Figure 37. Virtual ESR network
The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR.
A good trade-off is to design the network in order to achieve an R
Equation 28
where ∆IL is the inductor current ripple and V
voltage. It should be chosen higher than approximately 30 mV.
The new closed loop gain depends on C
that:
Equation 29
Where:
∆V
∆V
Output
Output
voltage
voltage
D
D
D
D
∆V
∆V
t
t
1
1
R1
R1
R1
R1
C
C
C
C
T node
T node
voltage
voltage
L
L
L
L
T
T
R
R
R
R
t
t
R
R
C
C
R
R
C
C
R
COMP pin
COMP pin
voltage
voltage
C
R
R
R
R
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
ESR
INT
C
C
INT
INT
C
C
INT
INT
Vr
Vr
FILT
FILT
FILT
FILT
>
INT.
=
2
V
π
t
t
g
RIPPLE
In order to ensure stability it must be verified
∆
×
RIPPLE
m
I
f
L
∆V
∆V
C
C
C
C
Z
INT
INT
INT
INT
×
1
1
R
R
R
R
R
R
R
R
R
R
R
R
−
V
2
2
2
1
1
1
2
2
2
1
1
1
COMP
COMP
COMP
COMP
Vr
is the overall ripple of the T node
OUT
R
OU
OU
T
T
OU
OU
T
T
out
FB
FB
FB
FB
Vr
Vr
Vr
Vr
gm
gm
gm
gm
ESR
+
+
V1
V1
V1
V1
given by:
Vr
Vr
Vr
Vr
Design guidelines
+
+
Comparator
Comparator
Comparator
Comparator
-
-
PWM
PWM
PWM
PWM
37/48