CDB-43L21 Cirrus Logic Inc, CDB-43L21 Datasheet - Page 29

• Manufacturer Part Number: CDB-43L21
• Description: EVAL BOARD FOR CS43L21
• Manufacturer: Cirrus Logic Inc

Specifications of CDB-43L21

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 96k
• Data Interface: I²C, SPI™
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS43L21
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1282; CDB-43L21

DS723A1
4.4.1
4.4.2
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
*MCLKDIV2 must be enabled.
Auto-Detect
Mode only)
(Software
Disabled
Enabled
MCLK
512, 768, 1024, 1536,
1024, 1536, 2048*,
2048, 3072
QSM
3072*
÷ 1
÷ 2
Figure 12. Master Mode Timing
MCLKDIV2
0
1
512, 768, 1024*, 1536*
Table 3. MCLK/LRCK Ratios
256, 384, 512, 768,
1024, 1536
HSM
÷ 128
÷ 128
÷ 256
÷ 512
÷ 2
÷ 2
÷ 4
÷ 8
Double
Speed
Quarter
Quarter
Speed
Speed
Speed
Single
Double
Single
Speed
Speed
Speed
Speed
Half
Half
256, 384, 512*, 768*
128, 192, 256, 384,
SPEED[1:0]
00
01
10
11
00
01
10
11
512, 768
SSM
LRCK Output
SCLK Output
(Equal to Fs)
128, 192, 256*, 384*
128, 192, 256, 384
DSM
CS43L21
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