CDB-43L21 Cirrus Logic Inc, CDB-43L21 Datasheet - Page 43

• Manufacturer Part Number: CDB-43L21
• Description: EVAL BOARD FOR CS43L21
• Manufacturer: Cirrus Logic Inc

Specifications of CDB-43L21

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 96k
• Data Interface: I²C, SPI™
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS43L21
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1282; CDB-43L21

CS43L21
Freeze Controls (FREEZE)
Default: 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to all control port reg-
isters without the changes taking effect until the FREEZE is disabled. To have multiple changes in the con-
trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then
disable the FREEZE bit.
DAC De-Emphasis Control (DEEMPH)
Default: 0
0 - No De-Emphasis
1 - De-Emphasis Enabled
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control.
Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample
rate of 44.1 kHz.
Analog Output Auto MUTE (AMUTE)
Default: 0
0 - Auto Mute Disabled
1 - Auto Mute Enabled
Function:
Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input
channel.
DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and imple-
mented for each channel. Note: The LIM_SRDIS bit is ignored.
DS723A1
43