R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 1010

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 26 Electrical Characteristics
Item
Oscillation settling time after leaving
software standby mode (crystal)
Oscillation settling time after leaving
deep software standby (crystal)
External clock output delay settling
time
External clock input low pulse width t
External clock input high pulse width t
External clock rising time
External clock falling time
(2)
Table 26.5 Control Signal Timing
Conditions: Vcc = PLLVcc = 3.0 to 3.6 V, AVcc = 3.0 to 3.6 V, AVccP = AVccA = AVccD = 3.0
Rev. 2.00 Sep. 16, 2009 Page 980 of 1036
REJ09B0414-0200
Item
RES setup time
RES pulse width
NMI setup time
NMI hold time
NMI pulse width (after leaving
software standby mode or deep
software standby mode)
IRQ setup time
IRQ hold time
IRQ pulse width (after leaving
software standby mode or deep
software standby mode)
Control Signal Timing
to 3.6 V, Vref = 3.0 V to AVcc, AVrefT = AVccA, Vss = PLLVss = AVss = AVssP =
AVssA = AVssD = AVrefB = 0 V
Iφ = 8 to 50 MHz, Ta = –20 to + 75 °C (regular specifications),
Ta = –40 to + 85 °C (wide-range specifications)
Symbol
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
t
OSC2
OSC2
DEXT
EXL
EXH
EXr
EXf
RESS
RESW
NMIS
NMIH
NMIW
IRQS
IRQH
IRQW
Min.
10
10
1
27.7
27.7


Min.
200
20
150
10
200
150
10
200
Max.





5
5
Max.








Unit.
ms
ms
ms
ns
ns
ns
ns
Unit
ns
t
ns
ns
ns
ns
ns
ns
cyc
Test Conditions
Test Conditions
Figure 26.3
Figure 26.4
Figure 26.5
Figure 26.6
Figure 26.7
Figure 26.8