R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 169

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
6.8
6.8.1
When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request with priority
over that interrupt, interrupt exception handling will be executed for the interrupt with priority,
and another interrupt will be ignored. The same also applies when an interrupt source flag is
cleared to 0. Figure 6.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared
to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to
activate the DTC, DTC activation and the interrupt exception handling by the CPU are both
executed. When changing the DTC enable bit, make sure that an interrupt is not requested.
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Usage Notes
Conflict between Interrupt Generation and Disabling
Figure 6.7 Conflict between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
Rev. 2.00 Sep. 16, 2009 Page 139 of 1036
TCIV exception handling
Section 6 Interrupt Controller
REJ09B0414-0200

Related parts for R0K561622S000BE