R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 180

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.4
The UBC does not detect condition matches in standby states (sleep mode, all-module clock stop
mode, software standby, deep software standby, and hardware standby modes).
7.4.1
1. The address condition for the break is set in break address register n (BARn). A mask for the
2. The bus and break conditions are set in break control register n (BRCRn). Bus conditions
3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the
[Legend]
n = Channels A to D
7.4.2
1. When specifying a PC break, specify the address as the first address of the required instruction.
2. The break occurs after fetching and execution of the target instruction have been confirmed. In
3. A break will not be generated even if a break before instruction execution is set in a delay slot.
4. The PC break condition is generated by specifying CPU cycles as the bus condition in break
[Legend]
n = Channels A to D
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address is set in break address mask register n (BAMRn).
consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the
CPU cycle setting is CPn = B'000, the PC break setting is IDn = B'00, or the read setting is
RWn = B'00.
corresponding channel. These flags are set when the break condition matches but are not
cleared when it no longer does. To confirm setting of the same flag again, read the flag once
from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0
to it after reading it as 1).
If the address for a PC break condition is not the first address of an instruction, a break will
never be generated.
cases of contention between a break before instruction execution and a user maskable interrupt,
priority is given to the break before instruction execution.
control register n (BRCRn.CPn0 = 1), PC break as the break condition (IDn0 = 1), and read
cycles as the bus-cycle condition (RWn0 = 1).
Operation
Setting of Break Control Conditions
PC Break