R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 219

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
8.5.3
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external address space area is accessed. Figure 8.8 shows an example of CSn (n
= 0 to 7) signal output timing.
Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For
details, see section 11.3, Port Function Controller.
In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins
CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should
be set to 1 when outputting signals CS1 to CS7.
In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a
reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7.
The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a
single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case,
the settings for the external bus interface areas in which the CSn signals are output to a single pin
should be the same.
Figure 8.9 shows the signal output timing when the CS signals to be output to areas 5 and 6 are
output to the same pin.
Chip Select Signals
Figure 8.8 CSn Signal Output Timing (n = 0 to 7)
Address bus
CSn
T
External address of area n
1
Bus cycle
T
2
Rev. 2.00 Sep. 16, 2009 Page 189 of 1036
T
3
Section 8 Bus Controller (BSC)
REJ09B0414-0200

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