R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 24

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 17 I
17.1
17.2
17.3
17.4
17.5
17.6
17.7
Section 18 A/D Converter ................................................................................. 715
18.1
18.2
18.3
18.4
Rev. 2.00 Sep. 16, 2009 Page xxii of xxviii
Features............................................................................................................................. 681
Input/Output Pins.............................................................................................................. 683
Register Descriptions........................................................................................................ 684
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.3.6
17.3.7
17.3.8
17.3.9
Operation .......................................................................................................................... 697
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
17.4.6
17.4.7
Interrupt Request .............................................................................................................. 711
Bit Synchronous Circuit.................................................................................................... 712
Usage Notes ...................................................................................................................... 713
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Features............................................................................................................................. 715
Input/Output Pins.............................................................................................................. 717
Register Descriptions........................................................................................................ 717
18.3.1
18.3.2
18.3.3
Operation .......................................................................................................................... 723
2
C Bus Interface 2 (IIC2)................................................................ 681
Restriction on Bit Manipulation when Setting the MST and
TRS Bits in Multi-Master Mode ....................................................................... 714
I
I
I
I
I
Slave Address Register (SAR).......................................................................... 695
I
I
I
I
Master Transmit Operation............................................................................... 698
Master Receive Operation ................................................................................ 700
Slave Transmit Operation ................................................................................. 702
Slave Receive Operation................................................................................... 705
Noise Canceler.................................................................................................. 706
Example of Use................................................................................................. 707
Module Stop Function Setting .......................................................................... 713
Issuance of Stop Condition and Repeated Start Condition ............................... 713
WAIT Bit.......................................................................................................... 714
Restriction on Transfer Rate Setting Value in Multi-Master Mode.................. 714
Notes on Master Receive Mode........................................................................ 714
A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 718
A/D Control/Status Register (ADCSR) ............................................................ 719
A/D Control Register (ADCR) ......................................................................... 721
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ............................................................... 685
C Bus Control Register B (ICCRB) ............................................................... 686
C Bus Mode Register (ICMR)........................................................................ 688
C Bus Interrupt Enable Register (ICIER)....................................................... 690
C Bus Status Register (ICSR)......................................................................... 692
C Bus Transmit Data Register (ICDRT) ........................................................ 696
C Bus Receive Data Register (ICDRR).......................................................... 696
C Bus Shift Register (ICDRS)........................................................................ 696
C Bus Format.................................................................................................. 697

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