R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 278

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 8 Bus Controller (BSC)
8.11
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access.
In addition, in the external bus released state, the BREQO signal can be driven low to output a bus
request externally.
8.11.1
In external extended mode, when the BRLE bit in BCR1 is set to 1 and the ICR bits for the
corresponding pin are set to 1, the bus can be released to the external. Driving the BREQ pin low
issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed
timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are
placed in the high-impedance state, establishing the external bus released state. For details on
DDR and ICR, see section 11, I/O Ports.
In the external bus released state, the CPU, DTC, and DMAC can access the internal space using
the internal bus. When the CPU, DTC, or DMAC attempts to access the external address space, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled.
If the BREQOE bit in BCR1 is set to 1, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When the CPU, DTC, or DMAC attempts to access the external address space
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
• When SCKCR is written to for setting the clock frequency
If an external bus release request and external access occur simultaneously, the priority is as
follows:
Rev. 2.00 Sep. 16, 2009 Page 248 of 1036
REJ09B0414-0200
module-clock-stop mode
(High) External bus release > External access by CPU, DTC, or DMAC (Low)
Bus Release
Operation

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