R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 303

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
19
18
17
Bit Name
ERRF

ESIF
Initial
Value
0
0
0
R/W
R/(W)* System Error Flag
R
R/(W)* Transfer Escape Interrupt Flag
Description
Indicates that an address error or an NMI interrupt has
been generated. This bit is available only in DMDR_0.
Setting this bit to 1 prohibits writing to the DTE bit for all
the channels. This bit is reserved in DMDR_1 to
DMDR_3. It is always read as 0 and cannot be modified.
0: An address error or an NMI interrupt has not been
1: An address error or an NMI interrupt has been
[Clearing condition]
•
[Setting condition]
•
However, when an address error or an NMI interrupt has
been generated in DMAC module stop state, this bit is
not set to 1.
Reserved
This bit is always read as 0 and cannot be modified.
Indicates that a transfer escape end interrupt has been
requested. A transfer escape end means that a transfer
is terminated before the transfer counter reaches 0.
0: A transfer escape end interrupt has not been
1: A transfer escape end interrupt has been requested
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
generated
generated
requested
When clearing to 0 after reading ERRF = 1
When an address error or an NMI interrupt has been
generated
When setting the DTE bit to 1
When clearing to 0 before reading ESIF = 1
When a transfer size error interrupt is requested
When a repeat size end interrupt is requested
When a transfer end interrupt by an extended repeat
area overflow is requested
Rev. 2.00 Sep. 16, 2009 Page 273 of 1036
Section 9 DMA Controller (DMAC)
REJ09B0414-0200