R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 370

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 10 Data Transfer Controller (DTC)
Figure 10.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
Rev. 2.00 Sep. 16, 2009 Page 340 of 1036
REJ09B0414-0200
DTC activation request
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERG:
DTCCR:
DTCVBR:
[Legend]
CPU interrupt request
Interrupt source clear
Interrupt controller
vector number
to DTCERG
DTCERA
DTCCR
request
(memory mapped)
must be set to 1.
External device
External
memory
8
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to G
DTC control register
DTC vector base register
peripheral
On-chip
On-chip
On-chip
module
ROM
RAM
Figure 10.1 Block Diagram of DTC
Bus controller
DTCVBR
REQ
ACK
DTC
Activation
Register
Interrupt
control
control
control
Bus interface
MRA
MRB
SAR
DAR
CRA
CRB

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