R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 390

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Data Transfer Controller (DTC)
10.5.3
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. This function is performed regardless of short or full address
mode. Table 10.5 shows the transfer information writeback skip condition and writeback skipped
registers. Note that the CRA and CRB are always written back regardless of the short or full
address mode. In addition in full address mode, the writeback of the MRA and MRB are always
skipped.
Table 10.5 Transfer Information Writeback Skip Condition and Writeback Skipped
10.5.4
In normal transfer mode, one operation transfers one byte, one word, or one longword of data.
From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be
specified as incremented, decremented, or fixed. When the specified number of transfers ends, an
interrupt can be requested to the CPU.
Table 10.6 lists the register function in normal transfer mode. Figure 10.7 shows the memory map
in normal transfer mode.
Table 10.6 Register Function in Normal Transfer Mode
Note:
Rev. 2.00 Sep. 16, 2009 Page 360 of 1036
REJ09B0414-0200
SM1
0
0
1
1
Register
SAR
DAR
CRA
CRB
*
Transfer Information Writeback Skip Function
Normal Transfer Mode
Transfer information writeback is skipped.
Registers
Function
Source address
Destination address
Transfer count A
Transfer count B
DM1
0
1
0
1
SAR
Skipped
Skipped
Written back
Written back
Written Back Value
Incremented/decremented/fixed*
Incremented/decremented/fixed*
CRA − 1
Not updated
DAR
Skipped
Written back
Skipped
Written back