R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 482

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 16-Bit Timer Pulse Unit (TPU)
12.3.2
TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each
channel. TMDR register settings should be made only while TCNT operation is stopped.
Rev. 2.00 Sep. 16, 2009 Page 452 of 1036
REJ09B0414-0200
Bit
7, 6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name

BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)

R
7
1
Initial
Value
All 1
0
0
0
0
0
0

R
6
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
BFB
R/W
5
0
Description
Reserved
These are read-only bits and cannot be modified.
Buffer Operation B
Specifies whether TGRB is to normally operate, or
TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register,
TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to normally operate, or
TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Modes 3 to 0
Set the timer operating mode.
MD3 is a reserved bit. The write value should always be
0. See table 12.12 for details.
BFA
R/W
4
0
MD3
R/W
3
0
MD2
R/W
2
0
MD1
R/W
1
0
MD0
R/W
0
0