R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 735

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.5
In slave receive mode, the master device outputs the transmit clock and the transmit data, and the
slave device returns an acknowledge signal. Figures 17.11 and 17.12 show the operation timings
in slave receive mode. The reception procedure and operations in slave receive mode are described
below.
1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
(Master output)
(Master output)
ACKBT bit in ICIER and perform other initial settings. Set the MST and TRS bits in ICCRA
to select slave receive mode and wait until the slave address matches.
the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the
ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read).
(Since the read data shows the slave address and R/W, it is not used).
fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting
before reading ICDRR to be returned to the master device is reflected in the next transmit
frame.
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
User
SCL
SCL
Slave Receive Operation
[2] Read ICDRR (dummy read)
Figure 17.11 Slave Receive Mode Operation Timing 1
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Rev. 2.00 Sep. 16, 2009 Page 705 of 1036
Bit 2
6
Section 17 I
Bit 1
7
Bit 0
2
8
C Bus Interface 2 (IIC2)
[2] Read ICDRR
REJ09B0414-0200
A
9
Data 1
Bit 7
1
Data 2