R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 956

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 24 Power-Down Modes
24.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0)
When the input buffers for the P10/IRQ0-A to P13/IRQ3-A pins are enabled by setting the
DIRQnE bits (n = 3 to 0) in DSPIER to 1, the PnICR settings corresponding to these pins are
invalid. Therefore, note that external inputs to these pins, of which states are reflected on the
DIRQnF bits, are also input to the interrupt controller, peripheral modules and I/O ports, after the
DIRQnE bits (n = 3 to 0) are set to 1
24.12.7 Input Buffer Control by DIRQnE (n = 3 to 0)
If a conflict between a transition to deep software standby mode and generation of software
standby mode clearing source occurs, a transition to deep software standby mode is not made but
the software standby mode clearing sequence is executed. In this case, an interrupt exception
handling for the input interrupt starts after the oscillation settling time for software standby mode
(set by the STS4 to STS0 bits in SBYCR) has elapsed.
Note that if a conflict between a deep software standby mode transition and NMI interrupt occurs,
the NMI interrupt exception handling routine is required.
If a conflict between a deep software standby mode transition and IRQ0 to IRQ15 interrupts
occurs, a transition to deep software standby mode can be made without executing the interrupt
execution handling by clearing the SSIn bits in SSIER to 0 beforehand.
24.12.8 Bφ Output State
Bφ output is undefined for a maximum of one cycle immediately after deep software standby
mode is canceled with the IOKEEP bit cleared to 0 or immediately after the IOKEEP bit is cleared
after cancellation of deep software standby mode with the IOKEEP bit set to 1.
However, Bφ can be normally output by setting the IOKEEP and PSTOP1 bits. For details, see
section 24.8.4, Bφ Operation after Exit from Deep Software Standby Mode.
Rev. 2.00 Sep. 16, 2009 Page 926 of 1036
REJ09B0414-0200