R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 10

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

SuperH
SH-2A Enhancements
Higher Execution
Performance
• Superscalar gives
• SH-2A =
Faster Interrupt
Response Time
• SH-2: 37 cycles;
• SH-2A =
Denser Program Code Size
• Improved C compiler
Upward Code Compatibility
SuperH Code Efficiency
PowerPC
1.5x
at the same MHz
performance of SH-2
SH-2A: 6 cycles
response time of SH-2
and additions to
instruction set provide
25%
(32-bit variable)
MIPS64
SuperH
(16-bit fixed)
(32-bit fixed)
(32-bit fixed)
(32-bit fixed)
more performance
V830
code size reduction
ARM
6x
1/25
SuperH
the
SH-4
SH-3
SH-2
SH-1
®
the
RELATIVE
VALUE
Family of Microcontrollers & Microprocessors
C Object Size Comparison
ARM7
Relative Value
Relative Value
0.75
0.50
0.25
ARM9
ARM
0.5
1
0
6
5
4
3
2
1
0
Relative Value
0.75
0.50
0.25
1
0
XScale
SH-2 @ 50MHz
@50MHz
Intel
SH-2
TOP REASONS TO SELECT SuperH
NEC
SH-2
@160MHz
1.0
Toshiba
MIPS
SH-2A
4.8x
1.0
SH-2A @ 200MHz
1/25x
IDT
0.75x
SH-2A
@200MHz
SH-2A
PowerPC
6x
1.24
1.44
1.5
1.28
1.5
SH-4A Enhancements
Higher Performance
at Lower Power
Improved Micro-
Architecture
Improved FPU
Architecture
Larger Cache Size
Greater Bandwidth
Bus Architecture
Instruction Set
Architecture
I
The roadmap for the SuperH processor product
line is upwardly code compatible. This
compatibility enables a faster time-to-market
with further amortization of prior engineering
investment and preservation of previously
written software.
• Processor choice from 10 to 1080 MIPS
• Large selection of devices within each family
I
• 16-bit instruction length for high code
• Up to 40% less memory footprint than
• Up to 40% more data in cache than
• Twice the number of instructions loaded
density
32-bit instructions
32-bit instructions
on the SDRAM bus
Total upward code compatibility
Best code efficiency
32/32 KB I/O Cache
600 MHz @ 1.25V
10-Stage Pipeline
7-Stage Pipeline
103 Instructions
Set-Associative
3 Independent
SuperHyway
Superscalar
SH-4A
4-Way
Buses
16/32 KB I/O Cache
240 MHz @ 1.5V
5-Stage Pipeline
5-Stage Pipeline
Set-Associative
91 Instructions
Superscalar
Shared Bus
2-Way
SH-4
8