R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 17

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

• An interrupt request can be sent to the CPU on
• Various DMAC transfer requests are provided:
• Channel functions: different transfer modes
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• Transfer possible over any number of channels
• 3 transfer modes: normal, repeat, and block transfer
• One activation source can trigger a number of data
• Direct specification of 32-bit address space
• Activation by software allowed
• Transfer can be set in byte, word, or longword units
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• Connectable to the main CPU with parallel bus
• HIF boot function eliminates the need for boot ROM
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• Triangular-wave comparison-type 6-phase PWM
• Non-overlap times generated by timer’s dead time
• Toggle output synchronized with PWM period
• PWM output halted by external signal
• PWM duty programmable between 0 and 100%
• Output-off functions
• Adjustable carrier frequency for low switching losses
completion of the specified number of transfers
– External request
– On-chip peripheral modules (Transfer requests from the
– Auto-request (A transfer request is generated
can be set for each channel
transfers (chain transfer)
waveform output with non-overlap dead times
counters decrease torque pulsations/harmonics for
improved voltage utilization
and less audible noise
Data Transfer Controller (DTC)
Host Interface (HIF)
Motor Management Timer (MMT)
SCI, SCF, and TMU can be accepted on all channels.)
automatically within the DMAC)
SuperH Main On-chip Peripherals
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• Up to 12-phase PWM output with synchronous
• 2-phase encoder pulse up/down count
• Counter cascade mode to 32-bit counter
• High sink current (15mA) for 6 pins; can directly
• A/D converter trigger signal can be generated
• Dead time can be generated automatically
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• 4- to 32-channel 10-bit successive-approximation
• 2 channel 8-bit D/A converter
operation
drive opto-isolators
A/D converter
– Precise current detection for current control
– Three sample-and-holds with maximum conversion time
Multi-function Timer Unit (MTU)
Analog Interfaces
of 5.4 microseconds
Interrupt
request
memory
Flash
Main
CPU
Data Transfer Controller Block Diagram
controller
Interrupt
Main CPU bus
16 bits
Host Interface Block Diagram
DTC
service
request
Connectable with general bus
SH-2
RAM
RAM
HIF
On-chip 1KB RAM
SH7618
Channel n
SH7619
n + 1
n + 2
Ether-C
Cache
DMAC
E-
PHY
SH local bus
Source
Memory data
Destination
DMA Register
Source
Serial I/O
Destination
Memory
LAN port
Optional
Boot ROM
SDRAM
memory
Flash
LAN