R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1190

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Main Revisions for This Edition
Page 1162 of 1190
Item
3.3.2 Floating-Point
Status/Control Register (FPSCR)
3.5 FPU Exceptions
3.5.1 FPU Exception Sources
3.5.2 FPU Exception Handling
Section 4 Clock Pulse Generator
(CPG)
4.1 Features
(1) PLL Circuit 1
4.3 Clock Operating Modes
Table 4.3 Relationship between
Clock Operating Mode and
Frequency Range
Page
69
71
71
72
73 to
76, 78
to 83,
85
75
82
Revision (See Manual for Details)
Table amended
Title amended
Description amended
FPU exceptions may occur on floating-point operation
instruction and the exception sources are as follows:
Description amended
These possibilities of each exceptional handling on
floating-point operation are shown in the individual
instruction descriptions. All exception events that
originate in the floating-point operation are assigned
as the same FPU exceptional handling event. The
meaning of an exception generated by floating-point
operation is determined by software by reading from
FPSCR and interpreting the information it contains.
Also, the destination register is not changed when
FPU exception handling operation occurs.
Description amended
internal clock → CPU clock
Description amended
When this is done, the phase of the rising edge of the
bus clock is controlled so that it will agree with the
phase of the rising edge of the CKIO pin.
Description amended
Caution: Do not use this LSI for frequency settings
other than those in table 4.3.
Bit
17 to 12
11 to 7
6 to 2
Bit Name
Cause
Enable
Flag
Initial
Value
All 0
All 0
All 0
R/W
R/W
R/W
R/W
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
Each time floating-point operation instruction is
executed, the FPU exception cause field is cleared to 0
first. When an FPU exception on floating-point
operation occurs, the bits corresponding to the FPU
exception cause field and FPU exception flag field are
set to 1. The FPU exception flag field remains set to 1
until it is cleared to 0 by software.
As the bits corresponding to FPU exception enable
filed are sets to 1, FPU exception processing occurs.
For bit allocations of each field, see table 3.3.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010