R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1205

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
20.3.2 A/D Control/Status
Register (ADCSR)
20.5 Interrupt Sources and
DMAC Transfer Request
20.7.7 Note on Usage in Scan
Mode and Multi Mode
26.5 Usage Notes
28.2 Register Bits
Item
Page
885
897
902
1026
1078
Revision (See Manual for Details)
Note added
Notes: 1. Only 0 can be written to clear the flag after 1
Description amended
... set to 1 on completion of A/D conversion. Note that
the direct memory access controller (DMAC) can be
activated by an ADI interrupt depending on the
interrupt controller (INTC) setting.
... of data. To make the DMAC transfer all conversion
data, set the ADDR where A/D conversion data is
stored as the transfer source address,
of converted channels × 2 as the transfer byte count,
and continuous operand transfer or non-stop transfer
as the DMA transfer condition.
Description replaced
Description amended
4. If the UDTRST pin is asserted immediately after
Table amended
Register
Abbreviation
SCFCR_0
the setting of the UDTDO transition timing
switching command and the negation of the RES
pin, the UDTDO transition timing switching
command is cleared. To avoid this case, make
sure to put 20 tcyc or longer between the signal
transition timing of the RES and UDTRST pins.
For details, see section 26.4.3, UDTDO Output
Timing.
Bits 31/
23/15/7
RTRG1
is read.
Please note that ADF flag becomes "0" in
the following cases, too.
(1) Reading the state of ADF = 1 with CPU.
(2) Clearing ADF flag by having read ADDR
(3) Set of ADF flag according to A/D
(4) Writing 0 in the ADF flag with CPU
Bits30/
22/14/6
RTRG0
with DMAC
conversion end
Bits 29/
21/13/5
TTRG1
Bits28/
20/12/4
TTRG0
Bits 27/
19/11/3
Main Revisions for This Edition
Bits26/
18/10/2
RSTRG2
TFRST
Bits 25/
17/9/1
RSTRG1
RFRST
Page 1177 of 1190
the number
Bits24/
16/8/0
RSTRG0
LOOP
Module
SCIF