R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 368

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R0K572011S000BE

Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr

Specifications of R0K572011S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 11 Direct Memory Access Controller (DMAC)
11.4
11.4.1
There are two DMA transfer modes ⎯ cycle-stealing mode and pipelined mode. These modes are
selectable through the setting of the DMA transfer mode select bits (MDSEL) in DMA Control
Register A (DMCNTAn).
Figure 11.2 gives examples of how bus mastership alternates between the DMAC and CPU in
various DMA transfer modes.
(1)
Cycle-stealing transfer mode is selected when the DMA transfer mode select bits are set to "00".
In cycle-stealing transfer mode, the DMAC leaves at least one cycle between the read and write
access cycles of each single data transfer. During this interval, the CPU can access the same target
BIU as the source or destination of its own operations. For details on the BIU, see section 11.1,
Features.
(2)
Pipelined transfer mode is selected when the DMA transfer mode select bits are set to "01".
In pipelined transfer mode, DMAC activates the bus for read or write access, or both, on
consecutive cycles. Therefore, the CPU cannot access the target BIU as a source or destination
during single operand transfer.
Pipelined transfer through a single BIU is not possible either.
Page 340 of 1190
Cycle-stealing Transfer Mode
Pipelined Transfer Mode
Operation
DMA Transfer Mode
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010

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