R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 375

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
11.5
11.5.1
When the value H'0000 0000 is transferred from the working byte count register to the DMA
current byte count register (DMCBCTn) (all data has been transferred), the DMA transfer end
condition is fulfilled and one DMA transfer is complete.
The operations following detection of the DMA transfer end condition are as follows.
• DMA transfer end condition
• Interrupt request generation
• Output of DMA end signal
• Clearing the DMA transfer enable bit (DEN)
• Reloading the source address register
• Reloading the destination address register
• Reloading the byte count register
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
The DMA transfer end condition detection bit (DEDET) for the corresponding channel in the
DMA transfer end detection register (DMEDET) is set to "1".
An interrupt request is generated for the interrupt controller according to the settings of the
DMA interrupt control register (DMICNT) and the DMA common interrupt control register
(DMICNTA).
The DMA end signal (DTENDm) is output according the setting of the DMA end signal output
control bit (DTCM) in the DMA mode register (DMMODn) for the channel.
If the DMA transfer enable clear bit (ECLR) in DMA control register B (DMCNTBn) is set to
"1", the DEN bit in the DMA control register B (DMCNTBn) is cleared to "0", suspending any
subsequent DMA transfer for the channel.
If the DMA transfer enable clear bit (ECLR) is clear ("0"), the DEN bit is not cleared.
If the DMA source address reload function enable bit (SRLOD) in the DMA control register A
(DMCNTAn) is set to "1", the DMA current source address register (DMCSADRn) is reloaded
with the value in the DMA reload source address register (DMRSADRn).
If the DMA destination address reload function enable bit (DRLOD) in DMA control register
A (DMCNTAn) is set to "1", the DMA current destination address register (DMCDADRn) is
reloaded with the value in the DMA reload destination address register (DMRDADRn).
Completion of DMA Transfer and Interrupts
Completion of DMA Transfer
Section 11 Direct Memory Access Controller (DMAC)
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