R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 408
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 408 of 1222
- Download datasheet (8Mb)
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
[Legend]
x:
Page 380 of 1190
Bit
7 to 5
4, 3
2 to 0
Don't care
Bit Name
CCLR[2:0]
CKEG[1:0]
TPSC[2:0]
Timer Control Register (TCR)
Initial value:
Initial
Value
000
00
000
R/W:
Bit:
R/W
R/W
R/W
R/W
R/W
7
0
CCLR[2:0]
R/W
6
0
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 12.4 and 12.5 for details.
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = Pφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is Pφ/4 or slower. When
Pφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 12.6 to 12.10 for details.
Clock Edge 0 and 1
R/W
5
0
R/W
CKEG[1:0]
4
0
R/W
3
0
R/W
2
0
TPSC[2:0]
R/W
1
0
R/W
0
0
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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