R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 413
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 413 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
5
4
3 to 0
Bit Name
BFB
BFA
MD[3:0]
Initial
Value
0
0
0000
R/W
R/W
R/W
R/W
Description
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated in other than complementary PWM mode.
TGRD compare match is generated in complementary
PWM mode. When compare match occurs during the tb
period in complementary PWM mode, TGRD is set.
Therefore, set the TGIED bit in the timer interrupt
enable register_3/4 (TIER_3/4) to 0.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated in other than complementary PWM mode.
TGRC compare match is generated in complementary
PWM mode. When compare match for channel 4
occurs during the tb period in complementary PWM
mode, TGFC is set. Therefore, set the TGIEC bit in the
timer interrupt enable register_4 (TIER_4) to 0.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 12.11 for details.
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Page 385 of 1190
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